I understand using PWM variable block designed for the RT box we can exceed 5khz. However, in my case, I am generating PWM by using manually designed carrier and reference (And then let them compare by using compare block). The reason is because I have a topology which needs very complicated logic to do( Including changing carrier frequency for some specific carrier cycle).

Is there a way I can use these logic blocks but still have a high switching frequency with RT box? (In the simulation it is totally doable, so the logic design is 100% correct)

Thanks for answering, appreciate it.

As you may already know, when using a Digital Out to generate a PWM signal the number of possible duty cycles is limited by the discretization step size. In your example with a 5 kHz PWM for a 1usec step size 201 different duty cycles are possible. For a 5usec step size then only 41 different duty cycles are achievable.

For the PWM Out and PWM Out (Variable) blocks, the FPGA is used for carrier generation and so the PWM accuracy is decoupled from the discretization step size. For a 5 kHz PWM on the RT Box 1 ~26,667 different duty cycles are possible.

Therefore, if you cannot reduce the step size to achieve the desired level of accuracy with the Digital Out blocks then the alternative approach would be to dynamically change the frequency, phase, and duty cycle inputs to the PWM Out (Variable) block to replicate the behavior of your modulator.

So is that possible to have about 20Khz switching frequency if I use logic block rather than PWM output block?

Thanks for answering it.

Well, you can generate a 20 kHz PWM signal (50usec period), but your duty cycle resolution will be limited based on the discretization step size as described above. With a 1usec step size there are only 51 possible duty cycles (e.g. switch on for 0usec/50usec, 1usec/50usec, 2usec/50usec, and so on).

Is this accurate enough for your application? I cannot say, but you might see some unexpected results.

You can compare the continuous and discretized models using the CodeGen work flow to see how it impacts the performance of your system offline before using the RT Box. Refer to the RT Box tutorials if you are unfamiliar with the CodeGen workflow.

Thank you very much for answering it.

I am actually using the RT box pwm variable block, but I believe the design of this block has some issues that could cause the output signal to switch incorrectly. I think this 2.0 version of Rt box block has some design wrong…

What I got from simulation is totally fine, but when I immigrate to PWM output block it starts to switch incorrectly periodically. Like in my case the first 0.165 it switch correctly and the next 0.165s it went bad switching and then becomes normal again… I dont know why. If I input wrong reference and carrier signal, I should have wrong results from the beginning. But now its getting wrong at the middle, it is really confused…

I am sorry I cannot show the results here since this is our lab research, but if we could talk by email that would be definitely helpful and I can show you exactly what happened.

Please contact support@plexim.com with your question and any necessary supporting information.