Reducing Simulation Time for Large-Scale Circuits

I am currently working on a PLECS model in which the overall circuit size has grown significantly due to the inclusion of multiple subsystems and detailed component-level modeling. As a result, the simulation time has increased drastically, making time-domain simulations extremely slow and, in some cases, impractical for iterative analysis and controller testing.

I would like to seek guidance from the community on effective methods to reduce simulation time in the PLECS model I am working on . The model has been attached below . Any suggestions, references, or practical experiences on optimizing simulation performance in such scenarios would be highly appreciated.

Thank you in advance for your support.

TEST.plecs (185.8 KB) ( The associated .mat file is not being allowed to be attached here . )