Regarding gate falling edge delay and rising edge delay issues.

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1

Hi :slight_smile:

Currently, I am looking into the characteristics of igbt in a converter like the attached picture.

However, as shown in plot 1 of the currently displayed figure, the gate voltage applied to igbt instantaneously becomes 1 and then becomes 0 without delay.

I would like to add a rising edge delay and a falling edge delay to the gate waveform for accurate switching characteristics analysis.

As a result of checking, it seems that the fall and rise times are very short, as shown in the second picture.

In the original case, shouldn’t the voltage and current drop and rise after applying the gate waveform?

And how do we solve the problem of pole time and rise time not being applied even though the devices are connected?

How can i solve it?

1111.png
1111.png1920×1080 155 KB

1212.png
1212.png1920×1080 155 KB

2

Hello,

PLECS uses ideal switches with instantaneous turn-on and turn-off transitions for robust, fast simulations. So you are not going to see the non-ideal switching transitions that you can observe with physical switch models and SPICE-type tools, for example. For modeling switching losses one can provide accurate loss data via lookup tables, but this may be a different topic that what you are interested in. Let me know if you have any further questions.

Regards,

Kris