Dear experts：
I use RTBOX to generate PWM waveforms by comparing carrier and modulation waves, but sawtooth waves cannot be generated correctly. The sawtooth waveform is as follows.
Thanks in advance
Bestregards,
zhihao chen
The RT Box certainly can, but maybe your model cannot. It would be helpful if you could share it.
The best way to to generate a sawtooth waveform is to use the triangular wave block and set the duty cycle to 0 or 1.
Thank you for your reply. This is my PWM generation model.
PWM.plecs (14.6 KB)
By the way, the controller I use is RTBox3
In addition, I found that when the duty cycle is set to 0.5, there is no problem with generating triangular waves. But when I set the duty cycle to 0 or 1, the generated sawtooth wave will have problems.
You are generating a 10 KHz sawtooth signal with a sampling frequency of 30 KHz. This means that you only get 3 sample values per period. If used as a carrier for PWM, you’d only be able to generate 3 distinct duty cycles. This will become more obvious if you switch the curve type to ‘discrete’ in the scope (see here).
One obvious solution is to increase the sample rate to e.g. 300 KHz. However, for PWM generation, we strongly recommend to use the PWM blocks from the RT Box library. With these blocks, the carrier signal is generated on the FPGA with a resolution of 6.67ns (for RT Box 2/3). If you need more control over the generated PWM pulse, use the “PWM out (Variable)” block.
I’d recommend to watch the tutorial videos on the RT Box.
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Thank you for your reply. This is very helpful.
But the PWM (variable) block in the RT Box library cannot achieve the function I want because my modulation wave is very complex.
Can I disconnect the library link of the PWM component in the library and only use the carrier function within the component.
Just like the model I modified below, of course, this is just a simple demonstration, and I need to implement more functions than that.
PWMOUT.plecs (124.3 KB)
In addition, when using PWM components in the library, if the control cycle and switching cycle are not consistent, the generated PWM also has problems, and its cycle and duty cycle will be incorrect.
PWM2.plecs (18.3 KB)
For example, this type of PWM
For a single pulse within a CPU step, you can use the “PWM out (Variable)” block, set the option “Synchronization with model step” to enabled and use a sawtooth carrier. Then the phase input controls the turn on time of the pulse and the duty cycle the length of the pulse.
You cannot use the PWM blocks to generate arbitrary patterns with several pulses during one CPU step.
If you think the PWM block is not working as documented, please supply a model that demonstrates the effect.
The PWM logic is coded into the FPGA. The offline model in the PWM block reflects the code in the FPGA. If you change the offline model, the offline simulation will change but the realtime simulation on the FPGA will work as before.
You can model more advanced PWM pattern creation like you did, but the resolution will be limited to the CPU step size.