Simulate how oversampling factors affects HIL(hardware-in-the-loop) simulation

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Hello all,

I am working on a power simulation project. For part of it, I need to see how the oversampling factor of the switch affects the simulation output. I noticed that you guys have a RT-box product that actually does HIL simulation, but I was wondering if I could replicate the same on the software side as a first-step validation before deciding to get the RT-box

Currently, I have set up a Half-bridge LLC in the simulation, as shown in the picture below.
The two pulse function are running at 100khz at 0.5 duty cycle, with one of it have a phase delay of (1/(100e3))*0.5 second to avoid possible of short circuit in the circuit.

In an effort try to simulate how the HIL model will look like at a oversampling factor of 20, which is 2MHz iteration, I have set the ode solver to be fixed step at 1/2MHz size, as shown in the picture.

My question is, with the setup of the discrete step ode solver,
does it correctly simulate how the RT-box simulates at oversampling of 20( iteration at 2MHz)? In other words, does it sample/read from the PWM signal for both switch at every 1/2Mhz second, and does the ode solver once for dt = 1/2MHz?
Or could it be the software under the hood does an adaptive time-step adjustment and does a multi-smaller step ode iteration in 1/2MHz time period for one step? Because if that is the case, this probably won’t reflect how the result will look on an actual RT-box

Many thanks for considering my questions!

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The modeling approach taken here doesn’t align with the RT Box for a few reasons.

From the solver side, the PLECS Fixed-Step Solver uses interpolation to handle zero-crossing events that occur between the fixed time steps (e.g. diode turn-off). See the " Fixed-Step Simulation" section of the PLECS manual for more information. If you set the ZC Step Size to try to disable the zero-crossing detection, eventually you’ll get state-space discontinuity errors as there will be a large step-change in circuit values due to the missed zero-crossing events.

To have a true discrete model that will not use interpolation, I would suggest using the CodeGen workflow. See the “Plant Code Generation: Three-Phase 6-Pulse Thyristor Converter” demo model for an example. You would use the CodeGen model with a variable step solver, with just the code-gen system modeled at the defined step-size. This allows you to have better PWM resolution, which is then only sampled at the defined-step size in your discrete-time model.

Also note that for switch modeling the RT Box uses a few different approaches that enhance the resolution of the PWM sensing (sub-cycle averaging) or the Nanostep solver with a step sizes down to 4 nanoseconds.