First, for future visitors to this question I’d like to note that your modeling approach doesn’t align with how the PLECS RT Box represents the converter, and this model is for your own independent study as we discussed in a previous forum post.
Regarding the error in your model, you can always compare a the code generation output with the output of a variable step solver, by changing your solver settings. You’ll notice you have a 40 MHz oscillation on your secondary voltages which cannot be captured at a 3 MHz sampling frequency but ends up manifesting as a DC error. Adding the capacitors also makes your system stiff.
