The modeling approach taken here doesn’t align with the RT Box for a few reasons.
From the solver side, the PLECS Fixed-Step Solver uses interpolation to handle zero-crossing events that occur between the fixed time steps (e.g. diode turn-off). See the " Fixed-Step Simulation" section of the PLECS manual for more information. If you set the ZC Step Size to try to disable the zero-crossing detection, eventually you’ll get state-space discontinuity errors as there will be a large step-change in circuit values due to the missed zero-crossing events.
To have a true discrete model that will not use interpolation, I would suggest using the CodeGen workflow. See the “Plant Code Generation: Three-Phase 6-Pulse Thyristor Converter” demo model for an example. You would use the CodeGen model with a variable step solver, with just the code-gen system modeled at the defined step-size. This allows you to have better PWM resolution, which is then only sampled at the defined-step size in your discrete-time model.
Also note that for switch modeling the RT Box uses a few different approaches that enhance the resolution of the PWM sensing (sub-cycle averaging) or the Nanostep solver with a step sizes down to 4 nanoseconds.