I’d like the simulate the beahviour of a LLC converter using the RT-Box 1. For this purpose I’m using the full-bridge LLC model with full-bridge secondary rectification offered by PLECS with the idea of using the sub-cycle average model with averaging time of 1us (which will be the time step used by the simulator).
I am a problem right now:
The control signals are the relative on-times of the IGBTs with values between 0 and 1. They can be seen as the duty cycles of the individual IGBTs during the simulation step. They are computed by periodically averaging the digital gate signals over a fixed period of time. The problem is that the LLC is controlled in frequency and the duty-cycle is fixed @50%, hence the model doesn’t seem to be suitable for this kind of purpose. Am I missing something?
Also, even if I tried to build the project, I obtain an error regarding an “algebraic loop”. This makes me think that the model is not suited for real-time simulation? Unless I fix this algebraic loop manually of course (maybe by inserting a “Memory” block where needed?)
> The problem is that the LLC is controlled in frequency and the duty-cycle is fixed @50%, hence the model doesn’t seem to be suitable for this kind of purpose. Am I missing something?
The Sub-Step Event LLC model works with a variable switching frequency control approach. Key to this is having sufficient number of model calculations within a switching period. From the documentation, “The discretization step size (sample time parameter) should not be larger than one fifth of the switching period.” More accurate results will generally be obtained with higher Tsw/Tdisc ratios. One would also need to use the PWM Capture component from the PLECS RT Box library to sense the relative on-times of the incoming PWM signals.
> I obtain an error regarding an “algebraic loop”. This makes me think that the model is not suited for real-time simulation?
The algebraic loop may be due to your overall model structure or perhaps the components connected to the LLC input or output terminals, as the module is interfaced through controlled current sources. It seems you did not attach a model to your original post as intended. If you include the model I can provide some additional guidance.
Thank you for attaching the model. As suggested in the previous answer, there are some limitations on the electrical characteristics of what can be connected to the Sub-step event module terminals without introducing an algebraic loop.
From the component documentation: “Both sides of the converter have current source behavior and must be connected to positively biased capacitors or voltage sources.”
The resistors in series with the input and output of the LLC are problematic, along with the cap’s ESR.