Wire Selector in Module: FCHB

[nongbi]

Hi, I’ve been looking deep into the Demo: Flying Capacitor DCDC Converter, to specific, the FCHB Module, which contains the wire selector that connects to source of the lower leg switch

I understand that most wire selectors employ the setting of

Input Witdh: 1 & Output Indices: [ones(1, N)], as is shown in the pic

which means wiring an input with a width of 1 to N output also with a width of 1. This is rather straight in most paralling applications.

However, in the demo mentioned above, the WS in the FCHB module uses the setting of:
Input Witdh: N & Output Indices: [N:-1:1], which is a quite confusing. The following pic depicts what I translated in the setting, pls make sure I’m not mistaken

First, why is the Input width N rather than ones(1,N)? There are N blocks. And why the output indices [N:-1:1] rather than ones(1,N)? Why the first output wire has a width of N and so on? I’m really confused.

Also, rearranging the WS block results in a failed simulation. I simply moved the WS as is shown in the pic followed, could you tell me what really changed?

Thank you!

[wolfgang]

Your second drawing for Input Width: N and Output Indices: [N:1:1] is incorrect. The following schematic illustrates what the Wire Selector does for different settings:

So the Wire Selector in the Flying Capacitor Half Bridge is used to reverse the order in an N-phase wire. When you move the selector to the C+ terminal, you are effectively reversing the order of the externally connected N capacitors. These capacitors have different initial voltages, so reversing their order will lead to inconsistent initial conditions. To fix this, you will need to reverse the initial voltage vector as well e.g. by changing the parameter expression to fliplr(Vc_init).