« La petite constante de temps, souvent, ce sont les petites choses qui comptent le plus »
Prof. Hansruedi Bühler, EPFL
When designing a control loop, a key question is: how much control bandwidth can I achieve? There is a simple way to think about bandwidth limits. It reduces the whole problem to a single number: the effective delay T_{eff} (a.k.a “petite constante de temps”) [1,2].
This article builds the delay-based framework from first principles. It shows how the framework extends to nested loop architectures and validates the approach with measurements on real hardware. It also gives practical rules of thumb for bandwidth planning from the earliest stages of design.
An accompanying PLECS model to experiment with can be downloaded here:
Introduction
A typical digitally controlled power converter has four main blocks in a feedback loop. The digital compensator G_c(z) computes a duty cycle command. The PWM actuator G_a(s) converts that command into a switched drive signal. The plant G_p(s) is the power stage (inductor, capacitor, and load). The sensor H(s) measures the output and feeds it back.
Real systems introduce delays, shown in red in the diagram above. These include the ADC acquisition and computation time, the PWM update latency, and the sensor signal conditioning lag. These delays do not come from the plant. They come from the digital implementation. In a well-designed system they are small compared to the plant time constants, such as the LC resonance period of the power stage. But they are not negligible: their total effect sets the fundamental bandwidth limit of the loop.
A natural benchmark when tuning such a feedback loop is the step response of a second-order system:
Optimal damping. The left plot shows step responses for fixed bandwidth with different damping ratios \zeta. Too little damping gives a fast rise, but with overshoot and ringing. Too much damping removes the overshoot, but makes the response slower than necessary. The value \zeta = 1/\sqrt{2} \approx 0.71 is the tuning target used in this article. It gives a frequency response that is as flat as possible. In the time domain this gives a fast step response with a small overshoot.
From damping to bandwidth. Once damping is fixed, bandwidth is the remaining design choice. The right plot shows the effect of varying bandwidth at fixed optimal damping. Higher bandwidth reduces the response time and is desirable. At \zeta = 1/\sqrt{2}, the -3\,\text{dB} bandwidth equals the natural frequency exactly, \text{BW} = \omega_n.
In practice, the achievable bandwidth is limited by the delays in the loop. Any delay means corrections are based on past information. The faster the loop, the more that lag matters. Eventually, corrections arrive so late that they destabilize the loop. Once damping is fixed, the delays alone set the ceiling.
For analysis, it is convenient to combine all delays into a single effective delay T_{eff}, placed anywhere in the loop. The justification for why this is possible is provided below.
Sources of Delay
In any real control system, several elements introduce phase lag. Some are true pure delays: their phase lag grows linearly with frequency by construction. Unlike a pole, a pure delay affects only phase and adds no attenuation. Other elements are not pure delays in principle, but can be approximated as such within the control bandwidth (see Appendix A).
True Pure Delays
These elements are pure delays by nature:
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Computational delay: the time between sampling and the moment the actuator command is updated. This is a fixed latency from the digital execution sequence.
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PWM actuator delay: in a digitally controlled power converter, the PWM modulator is the actuator. A new duty cycle value only takes effect at the next switching period boundary. The delay depends on the modulator type and the timing of the compare register update. For a symmetrical carrier with synchronous sampling, this is typically T_s/2 on average. The exact value depends on carrier shape, sample point, and reload event.
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DAC output hold: in a digitally controlled peak current-mode converter, the outer voltage loop commands the peak current setpoint via a DAC. The DAC output is updated once per control period and held constant until the next update. This is a Zero Order Hold (ZOH) on the setpoint path, contributing an equivalent delay of T_s/2.
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Inner loop execution rate: in nested controls the output of an inner loop is held constant for one sample period T_{si}. This is equivalent to a ZOH and therefore a pure delay of T_{si}/2.
Elements Approximated as Pure Delays
Other elements are not pure delays in principle, but their phase lag within the control bandwidth is approximately linear in frequency. This is what a pure delay produces. Three contributors fall into this category:
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Sensor bandwidth: a current or voltage sensor with finite bandwidth behaves like a low-pass filter. Well below its cutoff frequency, its phase lag is approximately proportional to frequency, making it equivalent to a small pure delay. This approximation is derived in Appendix A.
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ADC input circuitry and acquisition: a small RC filter is typically placed at the ADC input to ensure stable driving of the sample-and-hold capacitor. The ADC also requires a finite acquisition time before conversion begins. The RC filter is a continuous low-pass filter. The acquisition window provides a brief averaging effect. Both cutoffs lie well above the control bandwidth, so together they contribute a small equivalent delay that can be absorbed into the computational delay total. Note that the ADC has no ZOH characteristic. Unlike a DAC, it does not hold its output; it feeds the sampled digital domain directly.
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Peak current control: a peak current control loop introduces a modulator pole. It is also possible to approximate this effect as a pure delay. Unlike the others, this delay depends on the operating point and varies with the slope compensation ramp [4,5].
These approximations hold as long as the control bandwidth lies well below the corner frequencies of these elements. In practice, this means placing sensor bandwidths and ADC filter cutoffs at least a decade above the target bandwidth, which is standard practice in power electronics control design.
The Effective Delay
Pure delays combine multiplicatively in the frequency domain, and add directly in the time domain. This property allows us to define an effective delay T_{eff} by collecting all true and approximated delay contributions:
This additivity is the key property that makes the framework useful. Every element in the signal chain contributes independently and linearly to a single number that governs the achievable bandwidth.
PWM Actuator Delay and Calculation Delay
In a digitally controlled application, the delay through the digital controller from continuous input to continuous output is dominant. It deserves special attention.
Two distinct delays must be considered: the calculation delay and the reconstruction delay. In power electronics, the PWM modulator is typically the actuator and reconstructor. It converts the discrete-time duty cycle sequence back into a continuous-time switched signal, with an associated delay as derived in PWM Modulator Delay: Analysis verified by PLECS.
Between the ADC start of conversion (SOC) trigger and the moment a new duty cycle value takes effect, the microcontroller must complete the ADC conversion, run the control algorithm, and write the result to the compare register. This window is the calculation delay T_{calc}. It is a true pure delay.
The effective calculation delay T_{calc,eff} depends on when the new compare value goes into effect. In MCU PWM peripherals, compare registers are typically double-buffered: writing a new value goes into a shadow register, which does not affect the active compare register immediately. Instead, the shadow register content is transferred to the active register and latched at a configurable event, typically carrier overflow or underflow.
Asymmetrical carriers have a single latch event per period, at the overflow or underflow where the carrier resets. A new duty value written to the shadow register takes effect at the next reset, one full period away (T_{calc,eff} = T_{pwm}). Additionally, there is a reconstruction delay of the modulator that depends on the duty cycle: D \cdot T_{pwm} for a trailing-edge modulator and (1-D) \cdot T_{pwm} for a leading-edge modulator.
Symmetrical carriers reach both a peak and a valley within every switching period. This gives two latch opportunities per period, spaced T_{pwm}/2 apart. The reconstruction delay resulting from symmetrical modulation is T_{pwm}/2. The modulator delay does not change as a function of duty cycle or if the duty cycle is applied at an overflow or underflow event. What matters is whether T_{calc} is short enough to meet the nearer of those two deadlines:
- Deadline met (T_{calc} < T_{pwm}/2): the shadow register is updated before the next latch event. The new duty takes effect half a period later and T_{calc,eff} = T_{pwm}/2.
- Deadline missed (T_{calc} \geq T_{pwm}/2): the nearer latch event passes before the calculation is complete. The next opportunity is a full period away and the effective calculation delay doubles to T_{calc,eff} = T_{pwm}.
The transition is discontinuous: missing the deadline by even one clock cycle doubles the effective calculation delay.
Therefore, in case of a symmetrical carrier with shadow loading enabled at both overflow and underflow:
When the deadline is met, this simplifies to:
This sum is typically the largest single contributor to T_{eff} in a digitally controlled power converter and is at the root of the achievable regulator performance. The PWM actuator alone sets an inherent minimum of T_{pwm}/2. It is important to keep T_{calc} short enough to meet the half-period deadline.
This deadline directly shapes how the control algorithm is structured. A common approach is to split computation into two stages, illustrated below for a PI controller with anti-windup. Let the integrator state be x_I[k]. The two stages at step k are:
Stage 1 (time-critical): compute and write to the shadow register before the T_{pwm}/2 deadline:
Stage 2 (non-time-critical): update the integrator state for use at step k+1, after the shadow register has been latched:
where u[k] is the saturated actuator output and the last term is the back-calculation anti-windup correction. Only Stage 1 must finish before the T_{pwm}/2 deadline. The integrator update and anti-windup correction are not timing-critical.
Example: Effective Delay of Buck Converter
The image below shows the PLECS model of a digitally controlled buck converter. The plant represents a physical test setup with the following parameters: L = 82\,\mu\text{H}, C = 430\,\mu\text{F}, R_L = 147\,\text{m}\Omega, R_C = 10\,\text{m}\Omega, and R_\text{load} = 5\,\Omega. Three quantities are measured: the input voltage V_{dc}, the output voltage V_{out}, and the inductor current I_L.
The model is configured for automatic code generation using the PLECS TI-C2000 Target Support Package (TSP). The controller subsystem, shown below, has three ADC blocks acquiring I_L, V_{dc}, and V_{out}, and a PWM block running at f_{sw} = 50\,\text{kHz} with a symmetrical carrier. The PWM block is configured with compare shadow register updates at both underflow and overflow (CmpShadowMode: Underflow and Overflow). The ADC is triggered at every carrier overflow (AdcTriggerMode: Overflow).
As discussed in the prior section, with the ADC triggered at carrier overflow and the compare shadow register reloading at both overflow and underflow, two latch opportunities are available per switching period, spaced T_{pwm}/2 apart. The ADC is triggered at overflow and fires the control interrupt, the calculation runs, and the new duty value is latched at the next underflow, provided the calculation completes within the T_{pwm}/2 = 10\,\mu\text{s} window. The PWM actuator then contributes a further fixed T_{pwm}/2 from latch to effect. Both terms are fixed discrete quantities, giving:
If the calculation misses the underflow deadline, the next latch opportunity is at the following overflow, one full T_{pwm} after the ADC trigger. The PWM actuator delay remains T_{pwm}/2, so the effective delay increases to:
To validate the T_{eff} approximation, the duty-to-output voltage frequency response was measured in simulation using the Embedded Frequency Response Analysis (EFRA) block, assuming T_{eff} = 20\,\mu\text{s}. This gives the plant transfer function as seen by the MCU, including the effects of regular sampling and aliasing, as discussed in PWM Harmonic Spectrum: Analog and Digital Controllers Compared.
The plot shows three curves:
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The continuous-time plant transfer function G_{vd}(f) (blue)
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The pure-delay approximation G_{vd}(f) \cdot e^{-j2\pi f T_{eff}} with T_{eff} = 20\,\mu\text{s} (green)
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The full discrete-time model including aliasing (orange dashed)
PLECS simulation results are overlaid as markers. In the phase plot, the linear -360^\circ \cdot f \cdot T_{eff} asymptote (green dashed) shows the unbounded phase lag predicted by the pure delay alone.
The pure-delay approximation matches the simulation closely across the control-relevant frequency range. Visible divergence occurs only at higher frequencies where aliasing becomes significant. This further validates the single T_{eff} approximation as a useful tool for loop gain analysis and bandwidth planning.
The comparison also highlights the accuracy of the PLECS offline models for PWM and ADC blocks.
From Effective Delay to Achievable Bandwidth
A PI controller is a natural choice for most digital controllers in power electronics and drives [3]. Its integrator ensures zero steady-state error, and its single zero allows shaping the loop response. Higher-order systems can be handled by a PID or cascaded PIs.
Once T_{eff} is known, the choice of tuning method depends on the nature of the plant. For power electronics and industrial drives, the Magnitude Optimum and Symmetric Optimum [6] are the two most common approaches and typically produce excellent results. Both methods account for the plant parameters when setting the regulator coefficients, but the achievable crossover frequency and bandwidth depend only on T_{eff} and the tuning method, not on the plant. The detailed tuning procedure, including how to determine the regulator coefficients from T_{eff} and the plant parameters, will be covered in a separate article.
When the plant has a stable, well-characterized pole, such as the R_L/L pole of an inductor current loop, the PI zero can be placed to cancel it. The loop reduces to an integrator in series with the effective delay, and the gain is set for \zeta = 1/\sqrt{2}. The derivation is in Appendix B; the resulting closed-loop bandwidth is:
When the plant is integrating, or has a pole that is slow, load-dependent, or otherwise unreliable to cancel, the PI zero cannot be used for cancellation. Instead it is positioned to provide phase boost, placed symmetrically around the crossover frequency. This is the natural choice for a voltage loop driving an output capacitor, where the plant pole 1/(R_{load}C) shifts with load. The derivation and required prefilter design are in Appendix C; with the prefilter in place the bandwidth is:
A setpoint prefilter F(s) = 1/(1 + 4T_{eff}\,s) is required to cancel the closed-loop zero introduced by the symmetric optimum. With the prefilter, the symmetric optimum achieves the same optimal damping \zeta = 1/\sqrt{2} as the magnitude optimum, but at a natural frequency two times lower for the same T_{eff}. The lower bandwidth is the price paid for handling an integrating plant with robust disturbance rejection.
Once the bandwidth is known, the closed loop can also be approximated as a pure equivalent delay T_{eq}, as derived in Appendix A. This is particularly useful for nested loop design, where a closed inner loop appears to the outer loop simply as an additional delay. The key results for both tuning methods are summarized in the table below.
| Magnitude optimum | Symmetric optimum | |
|---|---|---|
| Applies when | Plant pole is stable and cancelable | Plant is integrating or pole is uncertain |
| Typical example | Inductor current loop | Voltage loop (capacitor plant) |
| Setpoint prefilter | Not needed | Required: F(s) = 1/(1+4T_{eff}\,s) |
| \omega_n | 1/(\sqrt{2}\,T_{eff}) | 1/(2\sqrt{2}\,T_{eff}) |
| Crossover \omega_c | 1/(\sqrt{2}\,T_{eff}) | 1/(2\,T_{eff}) |
| Bandwidth | 1/(\sqrt{2}\,T_{eff}) | 1/(2\sqrt{2}\,T_{eff}) |
| Equivalent delay T_{eq} | 2\,T_{eff} (Appendix B) | 4\,T_{eff} (Appendix C) |
Nested Loops and Delay Accounting
A common control architecture places one loop inside another. An inner loop regulates a fast variable such as current or velocity. An outer loop regulates a slower variable such as voltage or position.
When the outer loop bandwidth lies well below the inner loop natural frequency (\omega_{n,outer} \lesssim \omega_{n,inner}/2), the closed inner loop appears to the outer loop simply as an additional delay. The outer loop effective delay is:
As discussed above, the inner loop equivalent delay depends on the tuning criterion used:
- Magnitude-optimum inner loop: T_{eq,inner} = 2\,T_{eff,inner} (Appendix B)
- Symmetric-optimum inner loop with prefilter: T_{eq,inner} = 4\,T_{eff,inner} (Appendix C)
Delays add up across nesting levels. This gives a systematic way to allocate bandwidth across a multi-loop system before committing to any specific hardware or controller design.
Rule of thumb: budget T_{eff,outer} \approx 2T_{eff,inner} as a starting point for a magnitude-optimum inner loop, or T_{eff,outer} \approx 4T_{eff,inner} for a symmetric-optimum inner loop, then add any additional delays at the outer level.
Example: Nested Voltage and Current Control of a Buck Converter
This section validates the delay framework on a physical buck converter. The controller is designed in PLECS, generated as embedded C code, and deployed to a Texas Instruments F29H85x LaunchPad. The controller subsystem is shown below.
The outer voltage loop measures $V_{out}$ via ADC-E and compares it against a pre-filtered setpoint (6 V reference). The voltage loop’s PI controller produces a current setpoint i_L^* for the inner current loop. The inner loop measures the inductor current I_L via ADC-A and outputs a duty cycle command u^*, normalized by the bus voltage V_{dc} (ADC-C) before being applied to the PWM block.
The inductor current is sensed using an AMC1302 isolated amplifier. Each ADC input is conditioned with a small RC filter: 20\,\Omega, 2.2\,\text{nF} on the current path and 56\,\Omega, 2.2\,\text{nF} on the voltage path. Both the amplifier bandwidth and the RC filter time constants contribute equivalent delays, accounted for in the breakdown below.
The inner current loop is tuned with the Magnitude Optimum: its PI zero cancels the inductor pole L/R_L, reducing the plant to an integrator plus delay, and the gain is set for \zeta = 1/\sqrt{2}. The outer voltage loop uses the Symmetric Optimum: once the inner loop is closed, the outer plant is an integrating plant (the output capacitor integrates the regulated current) in series with the inner loop equivalent delay. A setpoint prefilter F(s) = 1/(1 + 4T_{eff,outer}\,s) cancels the closed-loop zero from the Symmetric Optimum, restoring optimal damping on the reference response. Both controllers and the prefilter were designed in the continuous domain and discretized using the Tustin method, following Discretization Done Right. Each PI includes output saturation with anti-windup.
The PWM configuration matches the previous example: a symmetrical carrier at f_{sw} = 50\,\text{kHz}, with shadow register updates at both underflow and overflow, and the ADC triggered at carrier overflow. This gives a base effective delay of T_{pwm} = 20\,\mu\text{s}. Adding the sensor contributions:
| Contributor | Value | Notes |
|---|---|---|
| PWM + calculation | 20\,\mu\text{s} | Deadline met |
| AMC1302 amplifier | \approx 807\,\text{ns} | 295 kHz BW, 2nd order, \zeta = 0.7 (Appendix A) |
| Current RC filter | 44\,\text{ns} | 20\,\Omega \times 2.2\,\text{nF} |
| Total T_{eff,inner} | \approx 20.8\,\mu\text{s} |
The outer loop effective delay adds the inner loop equivalent delay (T_{eq,inner} = 2\,T_{eff,inner}, Appendix B), the outer ZOH (the current setpoint is held for one sample period), and the voltage path RC filter:
| Contributor | Value | Notes |
|---|---|---|
| Inner loop equivalent delay | 41.6\,\mu\text{s} | 2\,T_{eff,inner}; Magnitude Optimum (Appendix B) |
| Outer ZOH | 10\,\mu\text{s} | T_{pwm}/2; current setpoint held one sample period |
| Voltage RC filter | 0.1\,\mu\text{s} | 56\,\Omega \times 2.2\,\text{nF} |
| Total T_{eff,outer} (predicted) | \approx 51.7\,\mu\text{s} |
The closed outer loop approximates a second-order system with \zeta = 1/\sqrt{2} and \omega_n = 1/(2\sqrt{2}\,T_{eff,outer}), giving predicted values of:
Open-loop gain. The voltage loop open-loop gain is shown below, with measured data overlaid on the analytical model.
Measurement and model agree well across the full frequency range. The actual crossover f_c = 1729\,\text{Hz} is about 9\% above f_{c,SO}. This is expected: the SO formula uses a first-order approximation for the delay, which is slightly conservative on phase. The phase margin of 51.2° is close to the 53° the SO gives in the ideal continuous-time case [6]. The small reduction is due to the discrete-time implementation.
The crossover lies well above the LC resonance at f_0 = 859\,\text{Hz}. This matters for disturbance rejection. Load current steps excite the plant near f_0, where the LC filter has its highest impedance. Having gain well above unity through that region keeps the closed-loop output impedance low, so the controller corrects the output before a large voltage deviation develops. A crossover below f_0 would reduce loop gain where rejection is most needed.
Closed-loop response. The closed-loop voltage regulation response V_{out}/V_{out}^* is shown below, with measured data overlaid on the simulated model.
Simulation and measurement agree closely. The -90° phase crossing and the -3\,\text{dB} point coincide at \omega_n, making the bandwidth directly readable from the phase plot. Both show this crossing at approximately 1100\,\text{Hz}, consistent with the predicted 1090\,\text{Hz}. The effective delay recovered from the measurement is:
The measured T_{eff,outer} \approx 51\,\mu\text{s} agrees closely with the predicted 51.7\,\mu\text{s}, confirming that the delay breakdown framework correctly predicts the achievable bandwidth of a nested loop across both tuning criteria, simulation, and real hardware.
Tracking response. The simulated and measured voltage-loop step responses are shown below, further confirming the match.
Load-step response. A simulated 2x load step between 5\,\Omega and 2.5\,\Omega is shown below.
The output voltage recovers with a peak deviation of approximately 3\%. Whether this is acceptable depends on the application. Where tighter regulation is required, the delays in the control loop would have to be reduced, for example by increasing the switching and/or control frequency.
Summary
This article presents a delay-based framework for estimating the achievable bandwidth of digital control loops. The central idea is that every element in the loop, including ADC acquisition, computation time, PWM actuation, sensor filtering, and inner closed loops, contributes a delay. These contributions add directly into a single effective delay that governs how fast the loop can respond. By identifying and summing these delays, a designer can predict the bandwidth achievable for a given damping target and controller tuning method from the earliest stages of design, without needing a full simulation or hardware prototype.
The framework applies equally to single loops and to nested architectures. For nested loops, a key result is that a closed inner loop can itself be modeled as an equivalent delay from the perspective of the outer loop. This equivalent delay then adds directly into the outer loop’s effective delay, just like any other loop element. As a consequence, each inner loop closure roughly doubles or quadruples the effective delay seen by the next outer loop, and bandwidth decreases predictably with each level of nesting. This gives a systematic way to allocate bandwidth across a multi-loop system before committing to any specific controller design.
The methodology is validated at two levels: first through simulation using PLECS, and then on real hardware using a digitally controlled buck converter deployed on a Texas Instruments microcontroller. In both cases, the measured closed-loop bandwidth agrees closely with the prediction from the delay breakdown, confirming that the framework is a useful engineering tool.
Acknowledgments
I want to thank @Munadir_Ahmed and @Bryan_Lieblick for their thorough review of this article and the valuable feedback they provided.
References
[1] H. Bühler, Conception de systèmes automatiques, Presses polytechniques et universitaires romandes (EPFL Press), Lausanne, 1988.
[2] H. Bühler, Réglage de systèmes d’électronique de puissance, Volume 1 : Théorie, Presses polytechniques et universitaires romandes (EPFL Press), Lausanne, 1997.
[3] H. Bühler, Réglage de systèmes d’électronique de puissance, Volume 2 : Entraînements réglés, Presses polytechniques et universitaires romandes (EPFL Press), Lausanne, 1997.
[4] R. B. Ridley, A New, Continuous-Time Model for Current-Mode Control, IEEE Transactions on Power Electronics, vol. 6, no. 2, pp. 271-280, Apr. 1991.
[5] C. P. Basso, Simulation Demonstrates Impact Of Current-Loop Crossover Frequency On Stability, How2Power Today, January 2021.
[6] J. W. Umland and M. Safiuddin, “Magnitude and symmetric optimum criterion for the design of linear control systems,” IEEE Transactions on Industry Applications, vol. 26, no. 3, pp. 489-497, 1990.
[7] H. D. Venable, “The K-factor: A new mathematical tool for stability analysis and synthesis,” in Proceedings of Powercon 10, San Diego, CA, 1983.
Appendix A: Approximating Lag Elements as Pure Delays
The delay breakdown in this article includes two kinds of contributors: true pure delays, and elements that are approximated as pure delays. This section derives that approximation formally, establishes its range of validity, and states the two results used throughout the article.
The central idea is simple: a pure delay e^{-T_{eq}s} has a phase response that is exactly linear in frequency, \phi = -\omega T_{eq}, and unity magnitude at all frequencies. An element can be treated as a pure delay of T_{eq} whenever its phase is approximately linear and its magnitude is approximately flat, that is, well below the element’s characteristic frequency.
The figure shows both cases on normalized Bode plots. The exact responses (blue) and the pure-delay approximations (green dashed) are indistinguishable within the shaded validity region. Beyond the boundary, the phase approximation diverges rapidly. The pure-delay model should not be used outside this region.
An element can be treated as a pure delay of T_{eq} in a loop design provided the loop bandwidth is well below the element’s characteristic frequency, by at least a factor of 2.
This condition is almost always satisfied in practice. Sensors and input filters are deliberately chosen to be faster than the intended control bandwidth. The 4\zeta^2 \approx 2 bandwidth halving at each loop closure naturally keeps outer loop bandwidths below the inner loop \omega_n/2.
First-Order Lag
A first-order lag with pole at \omega_p = 1/\tau has the transfer function:
Its phase is \phi(\omega) = -\arctan(\omega\tau). For \omega \ll \omega_p, the small-angle approximation gives:
This matches exactly the phase of a pure delay e^{-\tau s}. The approximation is valid to within a few degrees for \omega \lesssim \omega_p / 2, at which point the exact phase is -\arctan(0.5) \approx -26.6° against the approximation’s -28.6°, an error of about 2°.
A first-order lag 1/(1+j\omega\tau) can be treated as a pure delay T_{eq} = \tau = 1/\omega_p provided the loop bandwidth satisfies \omega_n \lesssim \omega_p / 2.
Second-Order System
A well-damped second-order system:
has a phase that, for \omega \ll \omega_n, is approximately linear in \omega. Expanding the phase for small \omega/\omega_n:
This matches the phase of a pure delay with:
For \zeta = 0.7 this gives T_{eq} = 1.4/\omega_n. Expressed in terms of T_{eff} using \omega_n = 1/(2\zeta T_{eff}):
The approximation holds to within a few degrees for \omega \lesssim \omega_n/2, at which point the phase error is approximately 3°.
A second-order closed loop with damping \zeta and natural frequency \omega_n can be treated as a pure delay T_{eq} = 2\zeta/\omega_n = 4\zeta^2 T_{eff} provided the outer loop bandwidth satisfies \omega_{n,outer} \lesssim \omega_n/2.
Appendix B: Magnitude Optimum and Equivalent Delay
Consider a plant P(s) = K_\text{plant} \cdot Z(s)/Q(s) with DC gain K_\text{plant}, stable and well-characterized poles and zeros, in series with the effective delay T_\text{eff}. Choosing the regulator as:
cancels all plant poles and zeros, reducing the open-loop transfer function to an integrator in series with the effective delay:
Cancellation is reliable only for poles that are stable, well-damped, time-invariant, and not nearly integrating [1,6]. Lightly damped, uncertain, or unstable poles must never be canceled. As shown in Appendix A, the pure delay is well approximated by a first-order pole for frequencies well below 1/T_\text{eff}, giving:
Closing the loop gives:
Comparing with the standard second-order form \omega_n^2/(s^2 + 2\zeta\omega_n s + \omega_n^2) and matching coefficients:
The magnitude optimum selects \zeta = 1/\sqrt{2} \approx 0.71: the unique damping ratio at which the closed-loop magnitude response is maximally flat, with no peaking for any \zeta \geq 1/\sqrt{2} and a peak appearing for any \zeta < 1/\sqrt{2}. This choice also maximizes bandwidth for a given T_\text{eff}. Substituting \zeta = 1/\sqrt{2} gives \omega_n = 1/(\sqrt{2}\,T_\text{eff}) and:
Applying the second-order equivalent delay formula from Appendix A, T_\text{eq} = 2\zeta/\omega_n, with \omega_n = 1/(\sqrt{2}\,T_\text{eff}) and \zeta = 1/\sqrt{2}:
The closed loop appears to any outer loop as a pure delay of twice the inner effective delay. This is the result used in the nested loop section.
Example. For a plant with a single real pole at s = -R_L/L and DC gain K_\text{plant} = 1/R_L, the cancellation regulator is a PI. The zero location, integration time, and gains follow directly from the magnitude-optimum result above:
Appendix C: Symmetric Optimum and Equivalent Delay
Consider an integrating plant with effective delay T_\text{eff}:
where the first-order pole approximation of the delay (Appendix A) has already been applied. Common examples are a current-driven capacitor and a torque-driven inertia [3]. A PI regulator with zero at \omega_z = 1/(a^2 T_\text{eff}) has the transfer function:
The gain K is chosen to place crossover at \omega_c = 1/(a\,T_\text{eff}), giving K = 1/(K_\text{plant}\,T_\text{eff}^2\,a^3). With a = 2 the three characteristic frequencies are spaced one octave apart:
The crossover sits at the geometric mean of the PI zero and the parasitic pole, equidistant on the log-frequency axis. This symmetry of the phase curve around \omega_c gives the criterion its name and guarantees maximum phase margin for this loop structure.
Note. The spacing ratio a corresponds to the K-factor of Venable [7], with K = a. The phase boost at crossover is \arctan((a^2-1)/2a) \approx 37° for a = 2, and increases monotonically with a. The value a = 2 is not set by maximizing phase boost but by the requirement \zeta = 1/\sqrt{2}: it is the ratio that satisfies this damping condition while placing crossover at the geometric mean of the PI zero and the parasitic pole [1,6].
The open-loop transfer function is:
Closing the loop gives:
Substituting K and factoring, the denominator is a third-order polynomial with a real pole at s = -1/(a\,T_\text{eff}) and a complex pair with \omega_n = 1/(2T_\text{eff}) and \zeta = 1/2. The numerator factor (1 + a^2 T_\text{eff}\,s) is a closed-loop zero that cannot be absorbed into the denominator. Without correction it causes approximately 43% overshoot on a reference step. A first-order prefilter is therefore a required part of the design:
It cancels the closed-loop zero, leaving a third-order response. The real pole at s = -1/(a\,T_\text{eff}) is fast relative to the complex pair and its effect is small; the response is well approximated by the second-order complex pair alone. The resulting bandwidth is:
This is half the bandwidth of the magnitude optimum for the same T_\text{eff}, which is the price paid for handling an integrating plant. The equivalent delay of the closed loop is obtained from the phase slope at low frequency (Appendix A). For the full third-order closed loop with prefilter this evaluates exactly to:
The closed loop appears to any cascaded loop as a pure delay of four times the effective delay, twice that of the magnitude optimum.
Example. For a capacitive plant with DC gain K_\text{plant} = 1/C and effective delay T_\text{eff}, the PI zero location, integration time, gains, and prefilter time constant follow directly from the symmetric-optimum result above: