Flyback converters remain one of the most widely used isolated power converter topologies, spanning applications from low-power phone chargers to auxiliary bias supplies and industrial power systems in the hundreds-of-watt range. Their simplicity, low component count, and ability to provide galvanic isolation make them an attractive solution across a broad range of applications.
Modern flyback converters are often controlled using highly integrated controller ICs that implement increasingly sophisticated control strategies to maximize efficiency, improve transient response, and meet stringent EMI requirements. While transistor-level IC simulation is important during silicon development, system-level converter design often requires a different modeling approach: one focused on behavioral accuracy, control-loop development, and simulation speed.
In this article, we explore how PLECS can be used to build progressively more sophisticated flyback converter models that match the engineering problem being solved. The focus is not on transistor-level IC simulation, but rather on behavioral controller models representative of those used during controller definition and system design.
This progression is well supported by PLECS, which enables behavioral, SPICE, and thermal modeling within a single environment. Rather than forcing a single high-fidelity model from the outset, the same schematic can be progressively enriched with parasitics, nonlinear device behavior, and electro-thermal coupling as design requirements evolve.
Choosing the Right Model
The three modeling levels explored in this article represent a deliberate trade-off between simulation speed, behavioral accuracy, and physical fidelity. The table below summarizes how each level maps to engineering use cases in the design process.
| Model Level | Primary Use Cases | Simulation Speed | Fidelity | Key Limitation |
|---|---|---|---|---|
| Control-oriented model | Controller development, compensation tuning, startup analysis | Fast | Functional | No DCM resonance; cannot model QR operation |
| Physics-augmented control model | QR controller development, valley-switching validation, DCM studies | Moderate | Behavioral + resonant physics | Instantaneous capacitor discharge at turn-on; switching losses inaccurate |
| Device-accurate verification model | Loss verification, thermal analysis, final design validation | Slow | Physical | High computational cost; not suited for iterative control development |
Each subsequent model resolves a specific gap in the previous one. The sections below build the models progressively, explaining which limitations motivate each modeling decision.
A common mistake in simulation-driven design is to start with the highest-fidelity model available. While this maximizes physical accuracy, it slows development by making every simulation expensive and difficult to debug. The workflow presented here instead begins with the simplest model capable of answering the current design question, and only increases fidelity when that question cannot be answered with the existing model.
Basic Flyback Model
The figure below shows a basic implementation of a flyback converter without any parasitic leakage inductances or capacitances. The input source is modeled as an ideal DC supply, while the output load is represented by an ideal resistor. The primary-side MOSFET and secondary-side diode are implemented using the standard semiconductor models available in PLECS. In behavioral mode, these devices are treated as ideal switching elements with simplified loss representations, rather than full semiconductor physics. This allows PLECS to achieve robust and computationally efficient switching simulations.
The flyback transformer is modeled using an ideal transformer with an ideal inductor connected across the primary terminals to represent the magnetizing inductance. The output filter consists of a capacitor with ESR included, since the resulting ESR zero has a strong influence on control-loop compensation and dynamic response.
Controller Architecture
The controller architecture modeled in this work represents a primary-side-controlled flyback converter. To maintain the galvanic isolation requirements common in flyback applications, a secondary-side feedback network based on a TL431 shunt regulator is used to generate an error reference voltage. Isolation between the secondary and primary sides is achieved using an optocoupler.
A variety of feedback configurations are possible for flyback controllers, including voltage-mode and current-mode implementations. In this design, the controller operates using a variable off-time modulation scheme representative of the MPS HFC0300 [1].
Increased output load current reduces the optocoupler feedback current, which lowers the voltage threshold applied to the off-time comparator. A lower threshold causes the ramp to trip earlier, shortening the off-time and raising switching frequency to deliver more power. The inverse applies at light loads: reduced load current raises the comparator threshold, extending off-time and lowering switching frequency.
This variable off-time mechanism forms the basis of the controller operation. Unlike a fixed-frequency PWM controller, variable off-time control allows switching frequency to follow the load naturally. This is particularly well suited to flyback converters. At light load, the reduction in switching frequency cuts switching losses, improving light-load and standby efficiency [2]. Variable-frequency operation also integrates naturally with QR control, where turn-on events must align to valleys in the resonant drain waveform rather than a fixed clock.
A single switching cycle combines two mechanisms, illustrated in the figure below. The off-time modulator ramp charges until it crosses the reference voltage derived from the optocoupler feedback, at which point the comparator output fires and turns on the primary switch. V_ds falls to zero and I_ds begins ramping up through the primary winding. The current limit ramp descends from its peak value over the on-time; when I_ds reaches it, the current comparator trips and turns the switch off. V_ds returns to the bus voltage, the off-time ramp resets and begins charging again, and the cycle repeats. The following subsections describe each mechanism in detail.
Off-Time Controller
The off-time controller consists of a comparator that compares the desired off-time reference against a generated timing ramp. The timing ramp is implemented using an ideal current source charging a capacitor, Cmod, at a fixed rate.
The ramp voltage is given by:
When the ramp voltage exceeds the reference voltage derived from the optocoupler feedback network, the comparator output initiates a new switching cycle by turning on the primary-side MOSFET.
To prepare for the next cycle, the ramp capacitor must be discharged after each switching event. This is achieved using the same logic signal that drives the primary switch. A minimum reset pulse width is enforced using a monoflop circuit ORed with the gate-drive signal to ensure complete capacitor discharge before the next charging cycle begins.
Two clamping circuits are included in the modulator.
The first enforces a minimum off-time. A diode in series with a voltage source is placed across the timing capacitor. Once the ramp voltage falls below the source voltage, the diode becomes forward biased and clamps the capacitor at a voltage corresponding to the minimum allowed off-time. This prevents very short off-time pulses at high load and is representative of how minimum off-time clamping would be implemented in a discrete prototype during the definition phase.
The second limits the maximum ramp voltage. An ideal current source charging an ideal capacitor in simulation will charge without bound; in practice, the current source is supplied from a bias rail and its output current is only regulated within a finite compliance range before naturally saturating at the supply voltage. A diode clamp replicates this behavior, preventing the ramp from accumulating to an unrealistic voltage between switching cycles.
Peak Current Modulation
The primary switch turn-off mechanism is implemented using a peak current modulation scheme. When the primary switch turns on, a current limit reference begins ramping downward from a peak threshold toward a minimum value at a fixed slope. The reference is continuously compared against the sensed I_ds; the switch is turned off when the sensed current reaches the ramp. The descending ramp also provides slope compensation: peak current mode control is prone to subharmonic oscillation when the duty cycle exceeds 50%, and a sufficiently steep compensating ramp stabilizes operation across the full duty cycle range.
For simplicity, the behavioral model assumes ideal current sensing using an ammeter component. In practical implementations, current sensing is typically realized using:
- sense resistors,
- current transformers,
- or integrated sense-FET structures combined with analog signal conditioning.
Since this model targets controller logic validation rather than sensing-circuit design, the ideal ammeter avoids introducing sensing-related dynamics that are outside the scope of the behavioral model.
The current limit ramp is modeled using a PLECS signal-domain integrator rather than the electrical-domain current source and capacitor approach used in the off-time modulator. Both are valid modeling techniques for the same underlying concept: a quantity that ramps at a controlled rate between bounds, but operating in different simulation domains. The off-time modulator uses an electrical circuit representation, which mirrors how such a circuit might be prototyped on a bench using discrete components. The current limit ramp uses the signal domain, which is more abstract but often more convenient when the physical implementation details are not the focus. This contrast is intentional: PLECS supports both approaches within the same model, and choosing between them is largely a matter of what level of physical detail is relevant to the design question being answered.
Limitations and Use Cases of the Basic Model
The basic flyback model provides an efficient platform for:
- controller development,
- compensation tuning,
- startup behavior analysis,
- transient response evaluation,
- and general functional validation.
For converters operating primarily in continuous conduction mode (CCM), the thermal modeling capabilities within PLECS can also be used to accurately model switching and conduction losses.
However, significant limitations appear once the converter enters discontinuous conduction mode (DCM).
Because the basic model contains no parasitic capacitances or leakage inductances, the drain-to-source voltage transitions instantaneously once the secondary current reaches zero and all transformer energy has been transferred to the output. In practice, this transition excites a resonance between the transformer magnetizing inductance and the parasitic capacitances present at the switching node.
This resonance produces the characteristic drain ringing observed in DCM flyback converters. Many modern controllers intentionally exploit this behavior to implement quasi-resonant (QR) valley switching, where switching events are aligned with a valley of the resonant waveform to minimize switching losses.
The resonant frequency is given by:
By turning on the primary MOSFET at the valley of the drain resonance, switching losses are significantly reduced and near-zero-voltage switching can be achieved under certain operating conditions.
Because the basic flyback model cannot reproduce this resonant behavior, it cannot accurately capture:
- QR operation,
- valley-switching behavior,
- realistic turn-on losses,
- switching-frequency modulation in DCM.
Its simplicity enables fast simulation and rapid iteration, but it cannot reproduce the resonant drain behavior required for QR control development.
The next modeling level addresses this by introducing parasitic capacitance, enabling resonant behavior and QR valley switching algorithm development.
Extending the Model to Support QR Operation
While drain ringing is often treated as a parasitic effect to be suppressed, QR controllers intentionally exploit it. Rather than turning on the primary MOSFET immediately after the off-time expires, the controller waits for a valley in the resonant waveform where the drain voltage is at a local minimum. At that point the voltage across the switch is reduced, lowering the energy dissipated during the turn-on transition and approaching zero-voltage switching under certain operating conditions.
To model this behavior, the flyback model must be extended to include the resonant dynamics present at the switching node.
As the converter enters DCM operation, the drain voltage exhibits a decaying oscillation formed by the interaction between the transformer magnetizing inductance and the effective parasitic capacitance at the switching node. This capacitance is typically dominated by:
- MOSFET
Coss, - transformer winding capacitance,
- PCB parasitic capacitance.
In the extended behavioral model, these parasitic capacitances are lumped into a single equivalent capacitor, Cp, connected between the drain node and the DC bus. A series damping resistor is included to reproduce the observed decay of the ringing envelope.
The actual damping arises from transformer winding AC resistance and core losses at the resonant frequency. A single resistor cannot reproduce the frequency-dependent behavior of either mechanism; a fitted RL ladder network would be more physically accurate [3]. The resistor used here is therefore a modeling convenience that reproduces the observed decay envelope rather than a direct representation of a specific loss mechanism. For applications where accurate ringing amplitude is important, the lumped resistor should be replaced with a ladder network fit to measured impedance data.
This approach also assumes a voltage-independent capacitance. When transformer winding capacitance dominates the drain node, this is often acceptable. However, MOSFET Coss is strongly nonlinear: it rises sharply at low drain voltages, which means the effective capacitance (and therefore the resonant frequency) changes with operating point. The ring frequency observed at light load, where the drain swings close to zero, will differ from that at heavy load. Because the QR controller derives its valley window timing from a fixed quarter-period estimate Tr/4, this operating-point dependence is a direct source of timing error that the extended behavioral model does not capture. If MOSFET Coss dominates the drain node capacitance, a nonlinear voltage-dependent capacitance model is necessary to reproduce the correct ring frequency across load conditions, at the expense of simulation speed.
This resonant network enables realistic DCM ringing behavior and forms the basis for QR valley detection.
Extended Controller Operating Cycle
The extended controller is built around four functional blocks. The off-time controller generates a pulse request once the programmed off-time has elapsed. This request is qualified by the QR valley window control, which monitors the drain ringing via the ZCD comparator and grants authorization only at resonant valleys. The primary switch modulator combines both signals to produce the gate drive: it arbitrates turn-on, enforces leading edge blanking immediately after the switch fires, and re-enables the current comparator once the blanking interval expires. The current limit comparator monitors I_ds against a descending current limit ramp and sends a turn-off signal to the modulator when the intersection is reached, ending the on-time. The following subsections describe each block in detail.
QR Detection and Valley Switching
Extending the basic controller to support QR operation requires detecting when a resonant valley is present and gating switching events accordingly.
In hardware, valley detection is typically performed using an auxiliary (bias) winding. The auxiliary winding provides a low-voltage scaled representation of the switching node waveform, avoiding the need for high-voltage sensing circuitry at the ZCD input. This voltage is fed through a resistor divider into a zero-crossing detection (ZCD) comparator referenced to ground. In DCM, the primary drain voltage rings around the input DC bus voltage. Each zero crossing of the auxiliary winding voltage corresponds to the drain voltage crossing Vin, which serves as the timing reference for valley detection. The relationship between these three signals is shown below.
The ZCD output feeds a finite state machine (FSM) that controls a single authorization signal gating when the primary switch is permitted to turn on. The FSM tracks the basic cycle phases: primary conducting, secondary conducting, and the DCM idle period. In CCM, where the off-time modulator fires before secondary current reaches zero, the valley logic is bypassed entirely and the switch turns on immediately. The QR detection path only activates once the secondary current hits zero and the drain begins ringing.
At each ZCD edge the machine opens a short authorization window timed to coincide with the valley of the resonant waveform, then closes it again across the rising portion. Switching is permitted only when this window is open, and the off-time modulator has simultaneously requested a new cycle. The window is offset from the ZCD edge by a fixed pre-window delay, sizing it to capture the valley rather than the zero-crossing point itself.
From each ZCD edge, the valley occurs a quarter-period later at Tr/4, with subsequent valleys spaced Tr apart. At light loads the resonant ringing is heavily damped and may decay before a sufficient number of ZCD crossings can be detected. To prevent the valley authorization logic from indefinitely blocking a switching request under these conditions, a maximum ring count is enforced. Once the counter is reached, the authorization is released unconditionally, allowing the switch to turn on regardless of valley position.
This FSM is a behavioral, system-level description of the QR valley switching feature. In a real controller IC, the same behavior could be realized using digital logic running at a high clock rate, or with analog circuitry designed to replicate the equivalent timing and gating behavior. The state machine is best understood as a requirements-level specification of what the controller must do, not a prescription for how it should be implemented.
Leading Edge Blanking
At turn-on, the primary MOSFET must discharge Cp, producing a sharp transient current spike. This spike is not related to energy transfer into the transformer but is instead a capacitive discharge event, often exacerbated in hardware by reverse recovery of the secondary-side and bias winding diodes, as well as currents sourced through snubber networks.
This current spike can falsely trigger the peak current comparator. To prevent this, leading edge blanking masks the current-sense signal for a fixed time after turn-on, ensuring the spike does not terminate the switching cycle prematurely.
Primary Switch Modulator
The off-time controller, QR valley switching algorithm, and current limit comparator each produce independent signals that must be combined into a single gate drive output. This is the role of the primary switch modulator.
The modulator is implemented as a state machine that arbitrates between the competing conditions. A switching cycle is initiated when the off-time modulator issues a pulse request and the QR authorization signal is asserted. Immediately after turn-on, the state machine enters a blanking state for a fixed duration, masking the current comparator output to prevent the turn-on current spike from prematurely terminating the cycle. Once the blanking period expires, the current comparator is re-enabled and the cycle is terminated when the sensed drain current exceeds the current limit threshold. The resulting PWM signal drives the gate of the primary MOSFET through an isolation gate drive circuit.
As with the QR valley window controller, this state machine is a behavioral description of the modulator logic. The same functionality could be implemented in hardware using discrete logic gates, a digital state machine clocked at a high rate, or equivalent analog timing circuitry.
Controller Responsibilities Across the Switching Cycle
One DCM switching cycle is illustrated below. During the off-time, V_ds rings around the input bus voltage as the magnetizing inductance resonates with the drain-node capacitance. The ZCD comparator detects these oscillations and the QR valley window control opens a brief authorization window at each resonant valley. When the off-time modulator ramp simultaneously crosses the reference threshold, both conditions are met and the primary switch turns on at a valley.
At turn-on, V_ds collapses to zero and a capacitive discharge spike appears on I_ds as Cp discharges through the switch. Leading edge blanking suppresses the current comparator output during this interval to prevent premature turn-off. Once blanking expires, the current limit ramp, which began descending from its peak value at turn-on, is compared against I_ds. When I_ds reaches the limit, the switch turns off, V_ds returns to the bus voltage, the off-time ramp resets, and the DCM ringing phase begins again.
Each phase of the cycle maps directly to a specific controller block. The off-time controller owns the off-time interval: its ramp charges until it crosses the reference threshold, at which point it issues a pulse request. Concurrently, the QR valley window control monitors the drain ringing via the ZCD comparator and asserts its authorization signal only at resonant valleys. The primary switch modulator requires both conditions to coincide before allowing turn-on, visible as the AND gate in the block diagram above.
At turn-on the primary switch modulator immediately enters its blanking state, absorbing the I_ds spike before the current comparator is exposed to it. Once blanking expires, the current limit comparator takes ownership of the on-time: the current limit ramp descends until I_ds reaches it, the comparator trips, and the modulator turns the switch off to complete the cycle.
Limitations and Use Cases of the QR Behavioral Model
The extended QR model significantly improves behavioral realism and enables:
- QR controller development,
- valley-switching validation,
- switching-frequency analysis,
- DCM operation studies.
However, adding Cp to enable QR operation introduces a key limitation when thermal modeling is required. PLECS switching-loss estimation for ideal switches relies on energy lookup tables indexed by instantaneous voltage and current at switching transitions. In this model, the discharge of Cp appears as a large current spike at turn-on, corrupting the current sample used for loss estimation. As a result, turn-on loss calculations become inaccurate when using standard lookup-based thermal models.
If switching loss estimation is required, either a custom loss model must be used that isolates magnetizing current from capacitive discharge current, or the model must be upgraded to SPICE-level device simulation.
The QR behavioral model introduces the minimum additional physics necessary to reproduce drain-node resonance and valley switching behavior. It remains computationally efficient and is well suited to controller development, but its treatment of capacitive discharge currents limits its usefulness for accurate switching-loss estimation.
SPICE-Level Device Modeling for Loss and Thermal Accuracy
The limitations above can be addressed using the PLECS SPICE simulation environment together with detailed semiconductor device models.
In this configuration, simulation is switched to SPICE mode via the simMode variable in the model initialization script. This variable configures whether the simulation runs using PLECS behavioral device models or SPICE-level device representations, allowing the same schematic to be used for both modeling levels without structural changes. In SPICE mode, the solver resolves full nonlinear device behavior at each timestep rather than relying on behavioral switching approximations.
This enables the use of manufacturer-provided device models, including:
- Primary MOSFET: IPD95R750P7 (Infineon)
- Secondary diode: V12P10 (Vishay)
- TL431 reference: Nexperia model
The logic-level MOSFET used for capacitor reset retains an ideal behavioral model rather than a SPICE representation. This illustrates a broader modeling principle: SPICE fidelity is applied selectively where physical accuracy matters, while paths where device physics have no bearing on the result are kept as ideal behavioral elements to avoid unnecessary simulation overhead.
Compared to the behavioral model, SPICE-level simulation enables direct computation of conduction losses, switching losses, device stress, and temperature-dependent behavior when coupled with thermal networks. This fidelity comes at a significant computational cost due to nonlinear capacitances, stiff switching dynamics, and the smaller timesteps required to resolve device transitions accurately. SPICE-based simulation is therefore best suited for final design validation, loss verification, and thermal analysis rather than iterative controller development.
Modeling Choices and Scope Boundaries
Every simulation model reflects a set of deliberate choices about what to include and what to leave out. The decisions made here are worth making explicit, since they define the boundaries within which the models are valid and the questions they are designed to answer.
Leakage inductance is not modeled. In a physical flyback transformer, leakage inductance causes a voltage spike at primary switch turn-off that must be managed with a snubber or active clamp circuit. This is a real and important design consideration in hardware. However, the primary objective of these models is controller development: characterizing the off-time modulator, the peak current limit, the QR valley switching algorithm, and the closed-loop dynamic response. None of these depend on the leakage spike or the snubber network behavior. Including leakage inductance and a snubber would add model complexity and simulation stiffness without contributing to the controller design goal, so it was deliberately excluded. As a consequence, the model also does not reproduce the ringing at primary switch turn-off seen in hardware, where leakage inductance rings with the drain-node capacitance during the switching transition. This turn-off ringing has no bearing on the QR valley-switching algorithms discussed in this article, which operate during the DCM idle period well after the turn-off transient has settled.
The SPICE model uses a fixed case temperature of 25°C. Full electro-thermal simulation, where device temperature feeds back into conduction and switching loss, is supported in PLECS but not implemented here. Prior to having hardware, a fixed case temperature is a practical approach for preliminary loss estimation. Choosing a temperature representative of worst-case operating conditions can provide useful insight into cooling requirements and heat sink sizing. Full thermal feedback can be added once a device and heat sink configuration have been selected and measured thermal data becomes available.
Conclusion
A robust flyback simulation workflow depends on matching model fidelity to the engineering question being asked. The three models presented here represent a deliberate progression: a behavioral model for controller development and compensation tuning, a physics-augmented model that introduces resonant drain dynamics to enable QR valley-switching control design, and a SPICE-level model for device-accurate loss and thermal estimation.
PLECS supports all three modeling levels within a single environment, allowing the same schematic to be progressively enriched as design requirements evolve. Behavioral elements, SPICE device models, and state machine controllers coexist naturally, and fidelity can be applied selectively where it matters. This approach ensures simulation remains a practical design tool at every stage of development rather than a computational bottleneck reserved for final verification.
Next Steps
The models presented here can be extended in several directions as the design matures.
On the power stage side:
- replacing the fixed case temperature with a full junction-to-ambient thermal network once a device and heat sink are selected,
- adding a nonlinear
Cossmodel if MOSFET capacitance dominates the drain-node resonance, - incorporating leakage inductance and an active clamp or snubber network to study their interaction with the controller,
- correlating behavioral and SPICE simulation results against hardware measurements,
- extending the SPICE model to support EMI prediction.
On the controller side:
- adding fault handling and recovery sequences such as overcurrent, overvoltage, and output short-circuit protection,
- modeling a startup sequence including soft-start and frequency or current limit profiling during initial ramp-up,
- replacing the hardcoded resonant ring frequency with a dynamic timing detection scheme; in a real implementation the controller would measure the ring period on the fly and adapt the valley window timing accordingly, rather than relying on a fixed value set at design time.
Appendix
The feedback network components (the TL431 shunt regulator and the optocoupler) are not the focus of this article. Brief descriptions of how they are modeled at each level are provided below for completeness.
TL431 Model
In the behavioral models, the TL431 is modeled as a voltage-controlled shunt regulator. When the voltage at the reference pin exceeds the internal reference threshold, the device conducts and pulls down the cathode voltage. The model captures this threshold behavior and output clamping without modeling the internal transistor-level circuit. The behavioral model used here is taken directly from the PLECS application note “Design of a TL431-Based Controller for a Flyback Converter”. It provides a full derivation and validation of the implementation. Readers interested in the model construction are referred to that resource [4].
In the SPICE-level model, the TL431 is replaced with a manufacturer-provided SPICE model (Nexperia), which captures the full nonlinear device behavior including dynamic response and operating-point-dependent characteristics.
Optocoupler Behavioral Model
The optocoupler is modeled as an LED diode on the input side driving a current-controlled current source on the output side, scaled by a fixed current transfer ratio (CTR). This captures the essential isolation and signal scaling behavior for feedback loop analysis. Dynamic effects such as bandwidth limiting and CTR variation with operating point are not modeled, which is appropriate for behavioral control-loop development where the optocoupler is treated as a static gain element.
References
[1] MPS HFC0300 Datasheet, Monolithic Power Systems.
[2] “Modeling Frequency Response of a Novel Pulse Width Modulated Flyback Control Scheme,” Power Integrations.
[3] R. Ridley, “Modern Magnetics Design,” Ridley Engineering.
[4] “Design of a TL431-Based Controller for a Flyback Converter,” Plexim Application Note.
Downloads
| File | Description |
|---|---|
| flyback_qr.plecs | Flyback QR simulation model |