Grid-Forming Inverter Stable in Offline Simulation but Unstable When Implemented in RT Box HIL Simulation

RT Box
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Hello

I am currently developing a Grid-Forming (GFM) inverter that will be implemented in a Hardware-in-the-Loop (HIL) environment. The HIL platform consists of an RT Box and a TI microcontroller. The plant model is executed on the RT Box, while the control algorithm is implemented on the TI microcontroller. The plant model consists of an average-model VSI (Voltage Source Inverter) with an LC filter connected to the grid through a grid impedance. The control system consists of a Virtual Synchronous Generator (VSG) controller, virtual impedance, voltage control, and current control loops. The modulation signals generated by the controller are transmitted from the TI microcontroller to the plant model via SPI communication. This approach is used due to the limited number of DAC channels available on the TI microcontroller. The inverter parameters (Kp, Ki, Rf, Lf, etc) are taken from a published journal reference. During offline simulation, the GFM model operates as expected. The inverter output power is able to track the reference power accurately, and the generated Uref signal is stable and behaves as expected.

Issue:
However, when the model is implemented in the HIL environment, the system becomes unstable. As shown in the attached file, there is video that the Uref signal exhibits unstable behavior. Initially, the Uref waveform follows the transient response observed in the offline simulation. However, after some time, the signal becomes unstable, then returns to its initial condition, and this behavior repeats periodically.

What could be the possible causes of this instability when the model is implemented in the HIL setup? Are there any specific aspects of the controller implementation, SPI communication, sampling rates, execution timing, or real-time constraints that I should investigate further?

Here I attached the plecs blockset model included with .m files simulations parameters below.

RT Box 2-TI F280049C configuration hardware:

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File: https://drive.google.com/file/d/1cHS4p734NeOfPgN84_DUNAsHtrcDYlzg/view?usp=sharing

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When your controller subsystem is modeled using a CodeGen simulation (i.e. the C-Code is generated and discretized) then it is unstable, while it is stable for a continuous time domain simulation. See the screenshot below showing the Vpcc feedback for this scenario.

This points to an issue in the parameter selection or control structure for you to debug. You can debug this in simulation. I can see Vdref jumping around. Adding more filtering in the Q calculation helps, but it still shows oscillations after a longer simulation run.

Other less critical issues:

  1. The integrator blocks in the APC and VSG do not have anti windup and do not have angle wrapping for the angle generation as noted in a comment on a previous post: “Another issue in your model worth pointing out is the role of the integrator blocks generating an angle. Those should have wrapping enabled from 0-2*pi. The issue will manifest for longer runs due to round-off error when a very small value (increment) is added to a large value (integrator state).”
  2. I suspect algorithm may not work well in the presence of noise, sensor error, or DC offset.

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Thank you for your response. It is very helpful and gives me a better understanding of the issue.