In the RT-Box manual, a timing diagram is given as follow. I want to determine the exact time delay in a converter system controlled by a RT-Box 2, so that I can model the system and design the parameters.
*1. In terms of period k, the voltage and current are sampled at first, as shown in the timeing diagram. And the delay between the sampling point and the beginning of period k is tAILat. What is the value of tAILat? According to the manual, a sampling rate of up to 1MHz can be realized (limited by firmware). Does it mean that tAILat is 1us? (CoderOptions - Target - Analog Input Sampling is set to “Minimize latency”).
*2. In terms of PWM out, update point is set on carrier minimum, and synchronization with model step is enabled. Does that mean the computation result of Period k will be loaded at the very beginning of Period k+1? And the carrier minimum is synchronized with the very beginning of each period?
All in all, the total time delay would be tAILat + 1Tsw(introduced by Period k) + 0.5Tsw (introduced by PWM), which is 1us + 1.5*Tsw. Is this correct?
