Inquiry Regarding Hardware-in-the-Loop (HIL) Simulation Issues

General
1

Hello, I have developed a hardware-in-the-loop simulation model for a single-phase cascaded H-bridge converter. In this setup, the main circuit is executed on an RT-Box 3, while the control algorithm is deployed on a TMS320F28069 DSP device. The model operates correctly in offline simulations within the PLECS software environment. However, during HIL execution, the controller fails to generate the correct sinusoidal pulse-width modulation signals, as illustrated in Figure 1. Consequently, the AC-side voltage and current waveforms exhibit significant distortions, as shown in Figure 2.

SPWM
SPWM1919×953 23.2 KB

Figure 1 SPWM (sinusoidal pulse‑width modulation) signal waveforms

VI
VI1919×975 31.7 KB

Figure 2 AC‑side voltage and current of the converter

I would like to inquire about the possible root causes of this issue and seek guidance on the appropriate diagnostic and troubleshooting procedures to resolve the observed anomalies.

Thank you for your attention. I look forward to your valuable suggestions. This is my model:

SigPET_3.plecs (206.4 KB)

3

Hi @Fish-of-Rhine,

I made a few changes to the model to improve the simulation:

  • I replaced the four individual half-bridge legs with a single vectorized Half-Bridge component. Since the number of legs is already a parameter, this change was straightforward and results in a more efficient simulation.
  • I moved the MCU LED into a separate task frame running at 0.5 s to offload it from the main CPU core. A similar optimization could also be applied on the RT Box side.
  • Changed the sampling of the LEDs to 0.5s.

After checking the results, I noticed that even during the offline simulation (without generated code), the exchanged values operate very close to the minimum and maximum voltage levels and are even clipped for short periods. This is definitely not ideal and could have a significant impact if any offset or noise is present.

image
image1920×1094 340 KB

I then generated code for both subsystems and ran them locally in Code Generation mode. I observed similar distortions there as well. However, after reducing the RT Box discretization step size to 2e-6 s, the distortions disappeared.

Unfortunately, I don’t have access to the exact hardware setup today to verify this on the target. I would therefore suggest trying these changes on your side and seeing whether they already resolve the issue.

SigPET_3_RC.plecs (196.1 KB)

4

Thank you for your improvements to my model. Today, I conducted a hardware-in-the-loop (HIL) simulation based on this model; however, unfortunately, the issue I previously raised still persists. The model I used is as follows:

SigPET_3_2.plecs (180.1 KB)

Since the RT Box reported an error “Encountered 5 consecutive overruns on core 0, terminating.” when the discretization step size was set to 2e‑6 s, I changed the step size to 5e‑6 s instead.

In addition, I had performed a HIL simulation of a PLECS model of a three‑phase two‑level converter with an LCL filter using the same hardware setup, and the waveforms were normal. This may help rule out hardware issues.

I am currently using PLECS version 4.8.4. Could the root cause of the problem be a model defect, software version, DSP type, or something else? I would be most grateful for your support and assistance.

5

I was able to run the simulation successfully on the hardware. I noticed the following main issues:

  • The pin assignment for PWM (Variable)1 was incorrect, which is why you see a constant high signal in Figure 1 of the original post.
  • The pin assignment for the ADC was also incorrect, resulting in an incorrect measurement of Vms.

In addition, I adjusted the signal scaling slightly to ensure that all values remain within the valid operating range.

For my tests, I ran the model on the FPGA of an RT Box 2 with an electrical simulation step size of 182 ns and a CPU step size of 2e-6 s. With this configuration, the simulation worked correctly, and the HIL results matched the offline simulation very well.

However, when I moved the electrical circuit from the FPGA to the CPU, the distortions immediately reappeared. In addition, the CPU occasionally experienced overruns even with a 2e-6 s step size. This indicates that running the electrical circuit on the FPGA using the FlexArray 2.0 solver is essential for this application.

To use this configuration, please update your RT Box to the latest Target Support Package and install the latest version of PLECS.

SigPET_3_RC_2.plecs (204.5 KB)