Compilation Issue of Hardware-in-the-Loop Simulation Model on RT Box 3

General
1

Dear Plexim Technical Support Team,

I have built a PLECS model of a three-phase four-stage cascaded power electronic transformer (PET) for hardware-in-the-loop (HIL) simulation based on the RT Box 3. To ensure complete gate drive signals, the microcontroller in this model only outputs the carrier signals for the input stage and the control signals for the DAB. The model performs well in offline simulation. However, during HIL simulation, when compiling the main circuit into the RT Box 3, the process gets stuck at:

“Step 92 of 94: Analyze transitions 92%”

After checking, the communication between the RT Box 3 and the simulation PC is normal. How can I improve my model? I look forward to your guidance.

The model is shown below:

Comp2.plecs (732.1 KB)

2

Your full bridges facing the grid use mixed ideal and non-ideal settings for the Switch Model parameter. Since you have a large number of bridges, only the non-ideal switch model can be used.

However, your model also contains Dual Active Bridges that you have rebuilt from discrete components. They will probably not work as intended since resonant topologies require very small step sizes, and your ratio of PWM period to step size (400 µs / 2µs) is way too small. Your best chance to run such a model is to split up the model on multiple RT Boxes and uses Nanostep modules instead.

3

Thank you for your valuable suggestions. I will improve my model accordingly.