Dear Plexim Technical Support Team,
I have built a PLECS model of a three-phase four-stage cascaded power electronic transformer (PET) for hardware-in-the-loop (HIL) simulation based on the RT Box 3. To ensure complete gate drive signals, the microcontroller in this model only outputs the carrier signals for the input stage and the control signals for the DAB. The model performs well in offline simulation. However, during HIL simulation, when compiling the main circuit into the RT Box 3, the process gets stuck at:
“Step 92 of 94: Analyze transitions 92%”
After checking, the communication between the RT Box 3 and the simulation PC is normal. How can I improve my model? I look forward to your guidance.
The model is shown below:
Comp2.plecs (732.1 KB)