TI C2000 PWM Variable Sequence Causes Shoot-Through in 3-Level T-Type Inverter

Coder TI C2000
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Hello everyone,

I am working on my master’s thesis, implementing a barycentric 3-level Space Vector Modulation (SVM) algorithm for a three-phase, 3-level T-Type inverter using PLECS Blockset and a TI LAUNCHXL-F28069M microcontroller.

I am currently investigating an issue with the TI C2000 PWM block’s Variable Sequence feature during offline simulation.

System configuration:

  • TI C2000 PWM generators: [1 2 3 4 5 6]

  • Symmetrical PWM carrier, 2 kHz

  • Complementary outputs

  • Dead time: 1 µs

  • Sequence: Variable (six independent seq commands)

  • RT Box HIL plant model using PWM Capture with sub-cycle averaging

  • Three-phase, 3-level T-Type inverter

Problem:

My SVM algorithm calculates an ordered switching-state sequence and corresponding dwell times. I convert these into six modulation indices (m) and six sequence-direction commands (seq) to reproduce the original symmetrical switching sequence.

The offline simulation behaves differently depending on the seq input:

  1. With seq = [1 1 1 1 1 1], the simulation runs successfully.

  2. When connecting the six dynamically calculated sequence commands, PLECS reports:

    Half-bridge shoot-through at t = 0.001255 s

  3. The issue also occurs when enabling dynamic sequence selection for phase A while keeping the remaining channels in Positive Sequence.

I have independently checked the ideal switching sequences in MATLAB at 5 kHz across 2,000 switching periods. Each gate requires at most one transition per ascending half-cycle, and the ideal PWM representation produces no logical mismatches at the checked intervals.

However, this verification does not include actual ePWM register updates, dead-time effects, or hardware timing.

My questions:

  1. Is it supported and safe to change the PWM Sequence dynamically between Positive and Negative for individual channels during operation?

  2. How are changes to the seq input synchronized with the PWM carrier and compare-register updates?

  3. Could changing the sequence direction introduce unsafe intermediate states, even with complementary outputs and 1 µs dead time?

  4. What is the recommended way to reproduce a precomputed symmetrical multi-state switching sequence on the F28069M using PLECS-generated code?

My goal is to preserve the original SVM switching sequence while avoiding CPU-intensive software switching.

Any guidance on the recommended PWM configuration or limitations of Variable Sequence would be greatly appreciated.

Thank you very much for your help!

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