I am performing DC motor control using the STM32 NUCLEO-F303RE. Initially, I am only testing the current loop, applying a constant current reference of 1.5 A. However, the trigger is not working as expected. I configured it to fire every time the ADC finishes reading, and the reading should start at the trough of the PWM carrier. However, as illustrated in the attached figure, the trigger (represented by the blue curve) occurs at the edge of the PWM (yellow curve in the figure), which causes the ADC to read practically the peak current value (pink curve in the figure). However, when I test in simulation, the trigger seems to work correctly, occurring in the middle of the PWM. If anyone can help me, I would be very grateful.
Thank you for your post and thank you for attaching your PLECS model!
I can reproduce some of the results that you are describing: Toggling PA5 is delayed with regard to the timer underflow event associated with the PWM block. When using a different duty cycle, it does not line up with the falling edge of the PWM signal. I believe that the root cause of this delay is our measurement methodology rather than the trigger chain itself. PA5 is toggled in the step function that is called every time the control task is executed (this function can be found in controle.c). A substantial amount of C code is executed before PA5 is toggled, which results in the delay that we observe. If I comment out some parts of the model (e.g. the blocks computing the discrete mean value), the delay decreases.
However, the ADC conversion takes place directly after the timer underflow event and should be sampling your current at the correct point. Do you have a separate test that determines whether or not the current sensing functions correctly?
Regarding the discrete mean values, I was using them to calibrate the value read by the ADC, but they are no longer necessary.
Regarding the current reading, I believe it’s incorrect because when I apply a current reference, the average current measured at the power supply shows a considerably lower value than the current read by the Plecs, and I believe the main culprit is the trigger.
I dug a little deeper to isolate the delay caused by the trigger chain from the delay caused by the control task execution. I am measuring a delay of around 2.2 [us], as shown in the oscilloscope screenshot below. The blue trace shows the PWM output. The yellow trace shows a GPIO that is set to high in the ADC ISR and set to low in the control task step function. The rising edge therefore occurs right after the ADC registers have been read.
To obtain this measurement, I modified your model. I will send you the modified model in a private message.
