Unexpected voltage difference circuits with parallel parasitic capacitance on diode

[shouyu]

Hello all,
I am currently working on simulating a simplified full-bridge LLC circuit.
Something I noticed in the simulation setting with the HIL model is that the steady-state final Vmout of the circuit has a difference of around 4Volt when I apply/don’t apply the 1e-9 parasitic capacitance in parallel with the diode.

Thus, my question is are the 4 Volt difference something expected in a state-space simulation engine? Or is there any addition parameters that I should setup to get a more accurate HIL model output?
I have also attached
Full-bridge-llc-simplified-hil.plecs (34.0 KB)
Full-bridge-llc-simplified-hil-with-capacitorx30.plecs (36.1 KB)
the plec circuit file if that helps.

Many thanks !

[Bryan_Lieblick]

First, for future visitors to this question I’d like to note that your modeling approach doesn’t align with how the PLECS RT Box represents the converter, and this model is for your own independent study as we discussed in a previous forum post.

Regarding the error in your model, you can always compare a the code generation output with the output of a variable step solver, by changing your solver settings. You’ll notice you have a 40 MHz oscillation on your secondary voltages which cannot be captured at a 3 MHz sampling frequency but ends up manifesting as a DC error. Adding the capacitors also makes your system stiff.