A question about modifying the synchronized sampling behavior in PLECS

PLECS
1

In PLECS, the comparison and sampling of PWM carriers are synchronously triggered at the global sampling instants.
As a result, even if a time shift exists between two PWM carriers, both carriers are sampled at the same instant.
When the carrier slope is nonzero, this synchronized sampling can lead to discrepancies in the comparison results, which appear in the control system as an equivalent PWM phase or duty-cycle error.

If an intentional time delay between PWM carriers is required in PLECS, is there a recommended method to modify or decouple this synchronized sampling behavior?

2

Hi jinlei96, it is a bit difficult to picture what you are trying to achieve without a model. From what I can gather maybe the PLECS library component Variable Phase PWM would be sufficient for what you are trying to achieve.

You can introduce an intentional phase delay between the PWM pulses via the ph port and see the performance of your control strategy to mitigate that phase shift?