Adjusting Sampling Time

General
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1

Is it possible to adjust the sampling time to 1usec, especially when using C2000 HIL simulation demos? If possible, how is this done? I have seen 50usec sampling time and wondering if I can achieve 1usec sampling time.

Thanks

2

Hi Hector,

Could you clarify whether you are referring to the microcontroller base task execution time?

The base task execution time depends on the complexity of the algorithm and the number of calculations the microcontroller must perform within the ISR call. In general, the simpler the task, the higher the ISR frequency can be.

I would encourage you to review the demo model “Dual-core Control of an On-Board Charger” included in the TI TSP. This model consists of two back-to-back converters:

  • The PFC control task is executed at approximately 30 µs.

  • The DAB control task is executed at approximately 20 µs.

Note that these control tasks are distributed across two separate cores, which enables both tasks to complete within their respective time budgets.

To configure the task rate, I recommend reviewing the relevant documentation and tutorialsL

Hope this helps!

3

Thank you for your reply. I checked through the demo model. Even though it opens my mind to what can be achieved with the PLECS RT box, I don’t get a clear explanation on how to adjust Ts to 1usec. However, I know that with simulation, I can do 1-usec sampling time, but it might not be necessary for real-time simulation. I mean, I should set my converter switching frequency to 1MHz, and every other control task should be completed within 1/1MHz sampling time.

4

Hi Hector,

I just wanted to clarify that the switching frequency and the control, or base task, frequency do not need to be the same. For example, you could operate at a 1 MHz switching frequency to reduce the size of your magnetics while running the control task at a significantly lower rate.

In practice, as you add more features and complexity to your system, the control task often needs to run more slowly. A 1 MHz ISR is typically not feasible on a standard MCU. In such cases, you may need to use advanced techniques such as leveraging the CLA, DMA, or even writing portions of the algorithm in assembly. Alternatively, an FPGA may be required.

In the OBC demo model I mentioned earlier, take a look at the parameters PFC_Fcontrol_Trigger_Divider and DAB_Fcontrol_Trigger_Divider. These parameters divide down the switching frequency of each converter to determine the control task ISR rate. For a 1 MHz switching frequency, a trigger divider of 10 could be a reasonable starting point, though you may need a larger divider depending on the complexity of your algorithm.

I also recommend reviewing the section “Advanced Explicit Configurations” in the C2000 documentation for additional details, as it helps clarify the relationship between switching frequency and control task ISR frequency.

Hope this helps.

5

Thank you for the insight!