HIL with TI C2000 (28379D) + RT BOX1 – How to control two converters using TI C2000 Target Support?

Coder TI C2000
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1

Hello everyone,

I am trying to perform HIL experiments using a TI C2000 (28379D) and an RT BOX1. I followed the TI C2000 Target Support demos under power supplies / onboard charger to control two converters with the C2000, but I haven’t been able to make it work properly.

I modified the task scheduling settings: Coder → Control → Scheduling set to multi-task, and I also added ADC B. However, I keep getting this error:

Only one Control Task Trigger block is allowed per CPU.

I apologize, but I am struggling to generalize from controlling one converter to controlling two converters. Any advice would be greatly appreciated.

Attached is my simulation (a back‑to‑back converter – the control logic is still crude, but my main goal is to understand how to implement control for two converters).

Thank you in advance.

2control_PWM.plecs (106.9 KB)

2

Hi jack2,

The C2000 code generation uses a rate-monotonic scheduler in which only a single ISR is used to trigger the scheduler. In PLECS, this is referred to as the Base Task (or Default Task).

All other tasks must execute at an integer multiple of the Base Task rate. Internally, the scheduler maintains counters to determine when slower tasks should run, which is why the task periods must be integer multiples of the Base Task period.

The next question is how and when this ISR should be triggered. In power electronics applications, this is typically handled by a PWM, ADC, or timer peripheral. In PLECS, this is configured using a Control Task Trigger component.

Since only one ISR is used per CPU, only a single Control Task Trigger is allowed per CPU.

Based on your model, the controller is currently configured as follows:

  • The PWM peripheral triggers an ADC start-of-conversion event at every overflow and underflow event.
  • The ADC then converts all channels associated with that ADC module (for example, ADC channels 0–2 on ADC A in your model).
  • Once all conversions are complete and the latest results are available for the controller, the ADC peripheral triggers the ISR.
  • This occurs because the ADC peripheral Task port is connected to the Control Task Trigger block.

To run two converters, you need to decide how the control tasks should be synchronized.

Option 1: Control tasks synchronized to each converter’s PWM

If each converter’s control task must be triggered relative to its own PWM timing, then you will need a dual-core processor and should place each converter’s control algorithm on a separate CPU core.

This allows each core to have its own ISR trigger and enables each controller to execute at the desired point within its respective switching cycle.

For an example of this approach, please see the C2000 On-Board Charger demo model.

Option 2: Single ISR with multiple tasks

If precise synchronization to each converter’s PWM is not required (for example, if you are implementing voltage control with heavily filtered feedback signals), then a single ISR can be used.

In this case, you can utilize:

  • multitasking, and
  • the Task Frame component

to specify the execution rate of the second converter’s control algorithm relative to the Base Task.

Hope this helps!

3

Thank you for your reply. As I mentioned in my question, I have referred to the on-board charger implementation, but neither ADC B nor multi-tasking worked well. Thank you for your suggestions.

4

Hi jack2,

Sorry, I had missed that part in your original post.

With the way your model is currently configured, there is no way for PLECS to determine which portion of the controller belongs to the “left task” and which portion belongs to the “right task”. As a result, everything in the model is assigned to the Default/Base Task (i.e., the “left task”).

The portion of the controller that you would like to execute on CPU2 via the “right task” must be explicitly identified so that PLECS knows it is intended to run at a different rate or on a different CPU altogether.

The way to accomplish this in your model is shown below:

image
image1736×928 194 KB

By partitioning the controller into separate task domains, PLECS can correctly assign the associated code to the appropriate task. If the task is assigned to a new CPU in the task scheduling tab then you can utilize another control task trigger block to determine when in your switching cycle you want to execute the task.

Hope this helps!