There are two error messages when I run your model. Firstly, you need to navigate into the Coder + Coder options… tab and then change the target to a C2000 device. Currently it is configured for a generic target. The second issue is the one you identified with the Memory component within the Powerstage Protection block.
Part of the issue is that you have your C2000 control logic at the top-level of your schematic. When the C2000 device is simulated in PLECS it will actually model the discrete behavior of your control system when simulated within a Code Generation Subsystem. When the components are at the top level the model is not executed in an atomic fashion.
I can propose two solutions while we look into a more robust solution to implement in the library component.
- Cut and paste your control logic within a Code Generation Subsystem from the PLECS library. Then open the Coder Options tab and configure the C2000 target and set the Discretization Step Size in the Scheduling tab. The advantages of this approach is a) the discrete behavior will be correctly represented and b) you can observe the behavior of the controller in offline simulations.
- You can place a Zero-Order Hold between the Digital In and Powerstage Protection block, as explained in this answer: Memory block for continuous signal - #2 by Bryan_Lieblick.
while trying to get this code to work for an RT box.
Note this code is for the C2000 target, so while the RT Box can be used for cHIL testing the RT Box cannot be used as the real-time target with C2000 blocks.