I’m trying to use the FPGA in RTbox3 to generate a high frequency sin wave at AnalogOut, as shown below. However, when I use oscilloscope to check the AnalogOut waveform, the step size is still CPU’s step size. What should I do to get a sin wave with FPGA’s step size?
Hi Zhang, What frequency are you targeting? What’s the overall application/goal?
The RT Box 3 Analog Outputs will update at the rate of the specified solver and DAC capability. For the CPU Solver that is every 1 usec. For the FlexArray solver the minimum step size is 48 nanoseconds, but the hardware DACs can only update every 200 nanoseconds.
Your use case model highlights something interesting - the FlexArray solver is exclusively for electric circuit simulation given the circuit state and external inputs (PWM signals, controlled sources, switch positions, etc). The sine wave input for the AC voltage source is not calculated on the FlexArray solver, but rather in an input from the sine wave calculation occurring on the CPU. If you look at the *.c code for the plant you will see code for the sine calculation.
If you would like to have an oscillation then it must be generated electrically. You can’t use something like an undamped LC network or Wien Bridge oscillator, as numerical solvers do not correctly represent purely imaginary oscillation modes. You’ll need a circuit that either filters a signal coming from the CPU (e.g. filtering sine wave or even square wave signal generated from CPU via passive circuits on the FlexArray) or a circuit that “actively” oscillates maybe like a van der pol oscillator (again you could build such a circuit out of op amps and have it execute on the FlexArray solver with the desired time-step).