I am generating the gate pulses in Simulink. I generate the phase-shifted gate signals by using Transport Delay blocks. The delay value is calculated from the required phase shift.
I have verified the gate pulses in both MATLAB/Simulink and PLECS, and they appear to have the same:
switching frequency
phase shift
pulse width
dead time
However, I have a problem with the simulation results.
The same converter works correctly when simulated completely in MATLAB/Simulink. But when I use Simulink for gate-pulse generation/control and PLECS for the power circuit, the output voltage is incorrect.totally distored give me proper approach to correct it
