Inquiries regarding RT Box HIL system

RT Box
1

Hello,

I’m currently configuring an RT Box–based HIL system that includes four flying capacitor boost converters.

As shown in the attached file, the system is structured in a master–slave configuration, where two flying capacitor boost converters are implemented per RT Box, and multiple RT Boxes are operated in parallel.

For the parallel connection between RT Boxes, we are using device coupling.
In this configuration, one side of the parallel connection is intended to behave as a current source, while the opposite side is configured to behave as a voltage source, in accordance with the general requirements for stable parallel operation.

However, we are encountering the following issue:

  • The model builds successfully without any errors.

  • But, when PWM signals are applied to the converters, all RT Box panels immediately report the warning: “Arithmetic overflow in FlexArray solver”

This warning appears consistently across all RT Boxes as soon as PWM switching is enabled.

At this stage, we would like to ask:

  • Whether there are specific modeling constraints or recommended practices for parallel RT Box configurations with switching converters

  • If there are any known limitations or additional requirements (e.g., impedance modeling, coupling strategy, or control assumptions) that must be satisfied to avoid FlexArray solver overflow in this type of setup

Relevant schematic files and configuration details are attached for reference.

We would appreciate your guidance on how this system should be modeled or configured to avoid the observed solver overflow issue.

Thank you very much for your support.

HV_BBU_Dual_RT_Box_wy.plecs (241.2 KB)

2

Hello Wooyoung,

The arithmetic overflow error message points towards an instability causing the value of the electrical circuit to exceeds the maximum or minimum allowed values of the solver.

There are a few main points to address beforehand:

  1. Have you validated the real-time performance with your controller of just one flying capacitor leg in real-time without system splitting? When I simulate your model in either sub-cycle average or switching mode I see the floating capacitor voltage collapse. One key constraint of the sub-cycle average model, as noted in the documentation, is the applied DC voltages must never become negative.
  2. Have you validated that you can run two flying capacitor legs in parallel (one FlexArray circuit) on the RT Box with your controller?
  3. This system can be simulated on one RT Box 2 or higher. Is there a particular reason why the model is split across multiple RT Boxes? Avoiding splitting when not necessary would be prudent.

A staged bring-up of each submodule, then multiple modules in parallel is recommended if you have not done so already.

Regarding decoupling - decoupling systems does induce a latency which can cause phase delay and ultimately an instability. The limits vary from application to application. You can also study this offline in PLECS to determine the maximum permissible latency. I can see the instability in your model offline when just running the second set of converters with the first disabled.

In your model I don’t see anything obviously incorrect or misconfigured but noted the delays are higher than they need to be. First, by placing the SFP connections in another task from the electrical circuit, the data is received by one core of the RT Box and sent to another. Use one CPU to start and if necessary to use subtasks, place the peripheral within the same task as the circuit. Secondary system has a delay in the voltage source interface circuit which is not required since the delay is modeled in the SFP components. The initial conditions are also critical as mismatched conditions can lead to large transient currents. Either start with the caps charged or discharged, but in your model the output is discharged while the floating capacitors are charged.

Regards,
Bryan

3

Hello Bryan,

Thank you for the detailed explanation and for reviewing the model so carefully — your comments were very helpful.

Based on your feedback, I agree that a staged validation approach is the most appropriate way forward. I will therefore proceed with the following steps and report the results accordingly:

  1. Validate real-time operation on a single RT Box with one flying capacitor leg.

  2. Extend the model to two flying capacitor legs in parallel on the same RT Box and verify stable operation.

  3. Scale the model to four flying capacitor legs on a single RT Box and confirm that stability is maintained.

I will share the corresponding model files and key results for each stage once the validations are completed.

Thank you again for your guidance.

4

Hello Bryan,

As a follow-up, a staged bring-up was performed starting from a single RT Box with a single flying capacitor (FC) leg.

Two models with identical topology and control were prepared:

  • A switched model for simulation-only validation

  • A sub-cycle average model intended for HIL

The only difference between the two models is the use of switching devices versus the sub-cycle average representation.

In the switched model used for simulation-only validation, no reverse DC voltage or flying capacitor voltage collapse is observed.

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However, when the sub-cycle average model intended for HIL is run in simulation mode, a negative drift of the flying capacitor voltage is observed. Starting from an initial value of approximately 400 V, the FC voltage ramps down, crosses zero, and continues to diverge negatively for the duration of the simulation.

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Attempting a no-load test with the averaged model results in the simulation not running due to numerical singularities, which appears to be inherent to the averaged FC formulation at zero current. Therefore, stability was evaluated under load conditions.

Based on this, my current understanding is that I’m using the PLECS flying capacitor sub-cycle average library blocks in line with the provided documentation and examples. However, given the observed behavior, I would like to ask whether there are any implicit constraints, assumptions, or usage conditions associated with this model that must be explicitly satisfied, and that I might currently be overlooking. In particular, I would appreciate your guidance on whether additional considerations regarding flying capacitor voltage handling are required when using the averaged formulation.

Once the single-leg averaged model behavior is clarified and stabilized, validation of parallel leg configurations will be carried out.

Please let me know if this interpretation aligns with your expectations, or if there are additional constraints you would recommend applying to the averaged FC model at this stage.

HV_BBU_One_FC_leg_SIM.plecs (113.2 KB)

HV_BBU_One_FC_leg_HIL.plecs (70.9 KB)

5

Your results agree with my expectations. The flying capacitor voltage in the switched model clamps at 0 V. The sub-cycle average model hits zero and continues towards a negative voltage.
The Flying Capacitor Half Bridge component help states “the applied DC voltages must never become negative”. In the sub-cycle average model the voltage doesn’t clamp at exactly 0 V.

If I set the load in your model to 500 Ohms then the capacitor voltage does stabilize to a non-zero value. The likely solution is that you’ll need an active balancing solution to operate under those load conditions.

6

Thank you for the explanation.

To isolate this effect, the model was modified under the assumption that the flying capacitor voltage is always properly balanced and maintained. Specifically, the flying capacitor was replaced with an ideal DC voltage source, and the validation was continued from the previous step under this assumption.

With a single FC leg, replacing the flying capacitor with a DC voltage source results in good agreement between the Sim and HIL models. From this result, the sub-cycle average formulation itself appears to be consistent in the single-leg configuration.

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When the model is extended to two FC legs, however, a discrepancy between the Sim and HIL waveforms appears again, even though the flying capacitor voltages in both legs are explicitly enforced by DC voltage sources.

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This leads to the following question:
Even under the assumption that each flying capacitor voltage is independently regulated and held constant, is the sub-cycle average model expected to scale consistently as the number of FC legs increases?

Any guidance on whether additional assumptions, constraints, or modeling limitations should be considered when increasing the number of FC legs would be greatly appreciated.

HV_BBU_Two_FC_leg_SIM.plecs (178.5 KB)

HV_BBU_Two_FC_leg_HIL.plecs (104.1 KB)

7

One difference between the SIM and HIL implementations of the model is that the Imperix modulation blocks are not simulating dead-time by default. It needs to be explicitly enabled. The dead-time is modeled in the SIM file.

The behavior is consistent whether the SIM or HIL models are used:

  • If dead-time is non-zero then the currents in each branch diverges but the branch with less current clamps at 0 A and the other branch carries the full load current.
  • If dead-time is zero then the branch with less current continues towards negative values, with increasing current on the other branch.