First, I’ll note there is a “Variable Phase PWM” block in the PLECS library. The underlying implementation is a C-Script, so it may be more difficult to understand, but the block is better documented than the phase shift PWM in the DAB demo model. The sampling behavior also better aligns with a digital phase-shift controller. See the component help for additional information.
Regarding the model you’re referencing, I would suggest adding additional scopes to analyze the block behavior. Please see the attached model which I used to generate the annotated scope capture below.
phaseshiftpwm.plecs (26.9 KB)
The block input is between -1 and +1 resulting in a phase shift of -180 or +180 degrees, respectively, between the primary and secondary gate signals. The output signals have a fixed duty cycle of 50%. One can see the “On carrier” and “Off carrier” waveforms are phase shifted 180 degrees from each other. This ensures the duty cycle is set to 50%.
The “Mpri” value (0.5 - m*0.25) sets the compare for when the primary turn-on and turn-off events happens. The turn-on is when (“On carrier” - “Mpri”) transitions from negative to positive, which generates a hit crossing event in the PLECS Solver. This sets the SR flip-flop for “G_pri” to a logical true output. The turn-off is when (“Off carrier” - “Mpri”) transitions from negative to positive, resetting the SR flip-flop for “G_pri” to a logical false output.
The “Msec” value (0.5 + m*0.25) value sets the behavior for the secondary turn on, which has an identical logic scheme but with a different compare value. Since the primary and secondary have the same carrier waveform, adjusting the compare values of both the primary and secondary results in a phase shift. Centering the compare values to 0.5 makes it easier to have both positive and negative phase shifts.
