I am using PLECS RT Box in RCP mode (controller only) to implement a modulation strategy based on a center-symmetric carrier (for a paralled T-type three-level inverter).
This modulation strictly requires:
center symmetry within each carrier cycle
consistent symmetry across multiple cycles
synchronized updates of fc', m, and ph'
Issue
1. No direct access to carrier-synchronous trigger
The only available trigger is via ADC trigger output (event signal).
However:
It cannot be directly used as a normal control signal
It requires Analog In / PWM Capture
I do not want to introduce ADC sampling in a controller-only setup
Question:
Can the internal carrier-synchronous trigger be accessed as a normal signal?
2. No multi-cycle update control (breaks symmetry)
To preserve center symmetry, I need:
fc', m, ph' to be updated once every N carrier cycles (e.g., 2 cycles)
Currently:
PWM updates once per carrier boundary
No way to enforce multi-cycle holding
This leads to:
mismatch between consecutive cycles
loss of symmetry
Question:
Is multi-cycle update (N-cycle hold) supported?
3. Symmetry loss in hardware
Due to imperfect synchronization:
small timing mismatch → asymmetry
device parasitics amplify imbalance over time
Question:
Is PWM Out (Variable) suitable for center-symmetric carrier modulation?
Any recommended architecture to preserve symmetry?
4. No user-defined carrier / trigger
My research requires:
custom center-symmetric carrier shapes
custom trigger/update timing
Question:
Is user-defined carrier or trigger logic supported?
5. Complementary PWM limitation
PWM Out mainly provides turn-on delay, but center-symmetric modulation requires:
strict complementary switching
symmetric dead-time
well-defined turn-off → turn-on timing
Question:
Is true complementary PWM supported?
Recommended way to implement symmetric dead-time in RCP?
Core need
Precise control of PWM update timing to preserve strict center symmetry across cycles, especially under variable frequency and interleaved operation.
Any guidance on architecture or limitations of PWM Out (Variable) would be highly appreciated.
Can the internal carrier-synchronous trigger be accessed as a normal signal?
No. It’s a virtual connection that configures triggering options in the FPGA.
If you want to synchronize the PWM to the control task, use the option “Synchronization with model step.” However, this option requires that your task execution period is an integer multiple of the carrier period, so you can only change the PWM frequency in integer steps.
Is multi-cycle update (N-cycle hold) supported?
Yes, if you place the PWM block in a task with an execution period that is half of the PWM carrier period. Option “Synchronize with model step” must be enabled.
Is PWM Out (Variable) suitable for center-symmetric carrier modulation?
The hardware is fixed. Level-shifters may have different rise and fall times, and they may even be temperature dependent. You will need to define measurable quantities and the tolerances that your application requires to decide if the RT Box is suitable for your setup or not.
Recommended way to implement symmetric dead-time in RCP?
The RT Box only offers turn-on delay and no turn-off delay. Instead of using a turn-on delay, you could use slightly different duty-cycles for the complimentary signals.
Dear zekez, the three things you mentioned that are required for your modulation (center symmetry within each carrier cycle, consistent symmetry across multiple cycles, and synchronized updates of fc’, m, and ph’) are provided by the RT Box.
The synchronization of PWM carriers is guaranteed if “synchronization with the model step” is enable in each PWM Out block, you do not need any trigger for synchronizing. Unless there is some information about your modulation that I am missing.
The inputs of the PWM Out block (m, fc’, and ph’) are always updated synchronously. If you need to use a different update rate than your PWM carrier period, as Oliver suggested, you can use the task frames.
The only point where you need to do some manual tweaking is the symmetrical dead time. But Oliver gave you the answer, adapt the duty cycles so the desired dead time is achieved.
See the attached model, I have even implemented a simple version of the symmetrical duty cycle approach Oliver mentioned.
Thank you for your help. However, when I run the model you provided, I encounter an error indicating that the power stage protection unit of PWM OUT needs to be assigned a value.
When I set it to unit1, the program crashes.
Could you please advise how this model is supposed to be configured or run correctly?