PWM Out (Variable) limitations for symmetric carrier modulation in RCP

RT Box
1

Background

I am using PLECS RT Box in RCP mode (controller only) to implement a modulation strategy based on a center-symmetric carrier (for a paralled T-type three-level inverter).

This modulation strictly requires:

  • center symmetry within each carrier cycle
  • consistent symmetry across multiple cycles
  • synchronized updates of fc', m, and ph'

Issue

1. No direct access to carrier-synchronous trigger

The only available trigger is via ADC trigger output (event signal).

However:

  • It cannot be directly used as a normal control signal
  • It requires Analog In / PWM Capture
  • I do not want to introduce ADC sampling in a controller-only setup

Question:

  • Can the internal carrier-synchronous trigger be accessed as a normal signal?

2. No multi-cycle update control (breaks symmetry)

To preserve center symmetry, I need:

fc', m, ph' to be updated once every N carrier cycles (e.g., 2 cycles)

Currently:

  • PWM updates once per carrier boundary
  • No way to enforce multi-cycle holding

This leads to:

  • mismatch between consecutive cycles
  • loss of symmetry

Question:

  • Is multi-cycle update (N-cycle hold) supported?

3. Symmetry loss in hardware

Due to imperfect synchronization:

  • small timing mismatch → asymmetry
  • device parasitics amplify imbalance over time

Question:

  • Is PWM Out (Variable) suitable for center-symmetric carrier modulation?
  • Any recommended architecture to preserve symmetry?

4. No user-defined carrier / trigger

My research requires:

  • custom center-symmetric carrier shapes
  • custom trigger/update timing

Question:

  • Is user-defined carrier or trigger logic supported?

5. Complementary PWM limitation

PWM Out mainly provides turn-on delay, but center-symmetric modulation requires:

  • strict complementary switching
  • symmetric dead-time
  • well-defined turn-off → turn-on timing

Question:

  • Is true complementary PWM supported?
  • Recommended way to implement symmetric dead-time in RCP?

Core need

Precise control of PWM update timing to preserve strict center symmetry across cycles, especially under variable frequency and interleaved operation.

Any guidance on architecture or limitations of PWM Out (Variable) would be highly appreciated.