Hi. During variable-frequency control, the frequency of the output PWM signal Q1 (f1) changes in real time. Based on signal Q1, I need to generate two additional PWM signals, S1 and S2, whose frequencies are both twice that of Q1, i.e., 2f1. Moreover, the relative phase positions between S1, S2, and Q1 must remain constant regardless of how the frequency changes.
I attempted to implement this function using the PWM (Variable) module on the TI C2000 platform. However, I observed that when the frequency f1 changes, the relative phase positions of S1 and S2 with respect to Q1 also shift.
Could you please advise on how to achieve this functionality?
Thanks for sharing the PLECS model. It is a bit challenging to follow the attached model, but the diagram you provided is quite clear. I have a few questions to better understand your setup:
Is Q1 the primary PWM signal that everything else is synchronized to?
Is S1 always on for the same duration as Q1?
Is S2 always toggled at the turn-off of Q1?
These details will help clarify your intended operation, and we can then suggest the best way to move forward.
Thank you for your reply. Q1 is the primary PWM signal to which everything else is synchronised.
The answer to the second and third questions is yes. Although the steady-state waveform was provided earlier, there is actually a transient process involved: the process by which the duty cycle gradually reaches a steady state. This process is shown in the attachment that has just been uploaded.
The switching pattern you are trying to achieve is an interesting challenge, and I’d be very interested to know the end application.
To generate this pattern, here is what I would suggest:
Set the base frequency of Q1 to F (for example, 10 kHz), and set the base frequency of S1 and S2 to F/2 (for example, 5 kHz).
Use a symmetrical carrier for Q1 and S1, and a sawtooth carrier for S2.
If the duty cycle of S2 can never exceed 50%, a symmetrical carrier could also be used, but you would then need to configure the action qualifier to:
set the PWM output at zero, and
clear the PWM output at CMP while the carrier is counting up, with no action while counting down.
Q1
Q1 is straightforward and can be controlled directly using:
the duty cycle input
the f input (to adjust the switching frequency relative to the base frequency)
S1
The way you have drawn it, using a symmetrical carrier makes this fairly simple, since no phase shifting relative to Q1 is required. The duty cycle is also independently controlled.
The main thing to define is the maximum allowed duty cycle for this channel.
From the two images you shared, my understanding is that the on-time of S1 can vary from 0 up to the same on-time as Q1, but only every other cycle. Because the frequency of S1 is half that of Q1, the duty cycle range for S1 would therefore be:
from 0 to 0.5 × D_Q1
S2
This is the more challenging part, because the exact phase relationship during transient conditions is not fully clear to me.
I configured the attached model to provide maximum flexibility in defining this phase relationship.
A few points:
During transients, I would expect the duty cycle to vary between 0 and 0.5, which ensures that the on-time coincides with the turn-off of Q1.
The main challenge is defining the phase relationship. You will need to establish a relationship between the duty cycle of Q1 and the phase shift of S2 to achieve the desired switching behavior.
The attached model shows what I believe should be the correct phase relationship for steady-state operation, but I am not fully familiar with all the constraints of your application, so this may need to be refined.
Since phase shift is applied to S2, its carrier must be synchronized using the PWM sync ports. In the attached model, S2 is synchronized to S1, assuming:
S1 and S2 operate at the same frequency
S1 has no phase shift relative to Q1
Here are the waveforms for both offline simulation and on the MCU configured for steady-state:
It is not guaranteed that the outputs Q1 and S1/S2 will are synced to each other. This is function of the System Clock Frequency (SYSCLK) and the Carrier frequency parameters. Lets assume the following:
The TBPRD register in TI C2000 ePWM modules defines the maximum value the time-base counter counts to, which sets the length of one PWM cycle. By changing TBPRD, you directly control the PWM frequency—larger values give lower frequency, and smaller values give higher frequency.
If F/2 leads to an odd value, the resulting PWM signals will not be in sync and drift over time.
Thank you for your reply. The simulation model you provided is correct when the frequency is fixed. However, it is worth noting that once the frequency changes, a phase shift occurs in the pulses within this model, and the phase relationships shown in the figure are no longer satisfied.During the frequency change, is it possible to maintain the relative phase relationship between the pulses?
Thanks for bringing this up. A couple of things are happening here:
The PLECS TSP only supports shadowing of all the registers (e.g., compare, period, etc.).
The TI ePWM module updates the TBPRD register only when the counter reaches zero (see the TBCTL[PRDLD] description).
In both the offline simulation and generated code, the first PWM period executes using the base carrier frequency specified in the mask via the Carrier Frequency [Hz] parameter.
As a result, the first period will always execute at the configured carrier frequency regardless of the input to f'. In the model I sent, this corresponds to 5 kHz and 10 kHz.
Unfortunately, if f' is not equal to 1, the current implementation can introduce a significant phase shift. As you can imagine, the 10 kHz PWM (Q1) will reach TBCTR = 0 before the 5 kHz PWMs (S1 and S2). This causes Q1 to load the new period value before S1 and S2 have an opportunity to update their frequencies, resulting in an apparent phase shift between the signals.
One possible approach is to synchronize the PWMs so that this apparent phase shift does not occur. For example:
However, even with synchronization enabled, you will still encounter glitches in the first pulse whenever f' is not equal to 1, for the same reason described above.
In the example below, the short pulse on Q1 occurs because the synchronization pulse generated by S1 resets the counter to zero:
This makes the configuration you are trying to implement particularly challenging.
Of course, the approach described above may not be the only way to solve the problem. There may be alternative implementations using action qualifiers, synchronization strategies, or other ePWM features that could mitigate some of the issues discussed here.
If you do find a solution, I would be very interested to hear what approach you ended up using.
Thank you very much for your thorough and insightful response. I really appreciate the time you took to break down the behavior of the PLECS TSP and TI ePWM module, and for pointing out the root cause of the phase shift and glitch issues.
Your expertise on this topic is impressive, and the suggestions regarding synchronization and alternative ePWM features are very helpful.
If I do find a working solution, I’ll be sure to share it with you. Thanks again for your support!
