I’m exploring the SPICE feature by trying to simulate a synchronous buck, but I receive an error message: “Unable to meet integration tolerances without reducing step size below smallest value allowed (3.55271e-15).“, as you can see in the below screenshot:
I’m probably doing something wrong, but couldn’t loacte it yet, the components netlists were downloaded from official manufacturer webiste (Infineon, most recent versions), and the rest of the components are ideal.
This will be impossible to debug without a simulation model as it can pertain to the parameters you’ve chosen and solver settings. Can you please share your model please?
Thanks for reaching out, please find the buck model attached, the main components are:
MOSFET: Infineon OptiMOS BSC026N08NS5
Driver: Infineon 1EDN TDI driver 1EDN8550B
The rest are just ideal components, with the PWM having frequency of 100 kHz, dead-time of 100 nSec, and output of 3.3 volts, to mimic controller’s output.
Thank you for posting your model. The main issue is in how you have configured grounding and the Vcc supply for your gate drivers. Look at Figure 8 of your gate driver datasheet. The GND of each driver should connect to the source of the FET. In your model they are both tied to the “GND” node which is basically floating as it has a high impedance path to the actual Spice circuit ground (defined by the PLECS ground symbol). The actual SPICE ground is connected to your gate driver IN+ and IN- terminals which are actually meant to be isolated.
The attached model shows the correct configuration. BUCK_SPICE_BL.plecs (79.5 KB)
Key points:
Ground established as common node between Vin and Vout.
Gate driver VDD supply is referenced to GND, which in turn is referenced to FET source pin.
For the high-side FET normally the voltage supply would be established with a bootstrap circuit (as shown in datasheet) but for PLECS we can just put an ideal source there.
Setup proper voltage drive configuration for IN+ and IN- terminals. Again, I matched the setup in Figure 8 since that’s how your hardware should be configured, but you could just as well connect voltage sources directly between the IN+ and IN- terminals for the purposes of this simulation.
I added resistance to the IN+ and IN- terminals. Doesn’t have a major impact but thought it wise since it’s called-out in the datasheet: “The two input resistors Rin1 and Rin2 are mandatory for correct operation of EiceDRIVER™ 1EDNx550 since this gate driver IC cannot be used as a standard low-side driver with IN- directly connected to GND pin.”
Added 50 mOhm of source resistance. If this resistance isn’t included then the operating point analysis will fail. You can also omit the source resistance if you change the “Initial conditions” setting in the Simulation + Simulation Parameters + SPICE tab to “off”.
Another solution to improve the likelihood of operating point convergence is to change the default initial conditions of the buck inductor current from “0” to empty. The default behavior of SPICE inductors and capacitors is to not have an initial condition (unless explicitly defined by the user). The operating point analysis can then pick any suitable value. This differs from the standard PLECS solver where inductors and capacitors require non-zero initial conditions. PLECS needs these as it does not do an operating point analysis to find these undefined values.
Used model references so that you only have to maintain one instance of each SPICE Netlist. I also added probes to these Netlists for Vgs, Vds, and Id for easy analysis in the bottom right-hand scope.
Many thanks for the extinsive, clear, and precise explanation and detailed correction, I really appreciate all the help and effort you put in this, not only it did solve my problem current problem, it also highlighted several others that I had and didn’t account for.
