Technical Support Request: PWM-Related Voltage Oscillations in RT-BOX 1 Real-Time Simulation of a PR-Controlled Three-Phase Inverter

[runxinYan]

Dear Plexim Technical Support Team,

I am conducting research on the impedance modeling and stability of a three-phase grid-connected inverter controlled by a Virtual Synchronous Generator (VSG) with cascaded proportional-resonant (PR) voltage and current control loops.

I am using PLECS 5.0.3 and RT-BOX 1 to investigate the inverter’s dynamic response to changes in grid inductance. However, I have encountered a significant discrepancy between high-accuracy offline simulations and real-time simulations.

1. System Configuration

The main system parameters are as follows:

• Real-time platform: RT-BOX 1

• Simulation software: PLECS 5.0.3

• DC-link voltage: 500 V

• Inverter-side filter inductance: 8 mH

• Filter capacitance: 10 μF

• Filter grid-side inductance: 2 mH

• External grid inductance: changing from 2 mH to 5 mH

• Grid frequency: 50 Hz

• PWM switching frequency: 10 kHz

• PWM signal delay: 100 μs

• Control strategy: VSG with cascaded PR voltage and current control loops

The PR controllers are implemented using continuous-time transfer function blocks. The entire control system, PWM generation, inverter, LCL filter, and grid are executed within a single RT-BOX 1.

Four analog output channels are used to display the three-phase PCC voltages and the grid-inductance switching signal on an external oscilloscope.

2. Problem Description

In the offline simulation, a variable-step solver or a sufficiently small fixed step size (2 μs) produces the expected results:

• With an external grid inductance of 2 mH, the three-phase voltages and currents are stable and nearly sinusoidal.

• When the grid inductance increases to 5 mH, significant voltage and current oscillations occur, with a dominant oscillation frequency of approximately 800 Hz.

However, when the model is discretized using a 10 μs fixed step size and deployed to RT-BOX 1, noticeable periodic voltage and current ripple appears even before the inductance change.

FFT analysis indicates an additional frequency component around 1 kHz under the initial 2 mH grid condition.

This behavior can also be reproduced in the offline fixed-step simulation. Therefore, the problem appears to be related to the numerical implementation of the switching inverter rather than solely to the analog output hardware.

3. Troubleshooting Already Performed

I have carried out the following tests:

Modification	Observed result
Variable-step offline simulation	Smooth voltage and current waveforms
Fixed-step, 10 μs	Significant periodic ripple
Fixed-step, 5 μs	Ripple noticeably reduced
Fixed-step, 2 μs	Ripple significantly reduced
Reduced PWM frequency from 10 kHz to 5 kHz	No substantial improvement
Replaced the original IGBT converter with three Half Bridge modules in Switched mode	Ripple remained
Changed floating-point format from double to float	No substantial improvement
Changed PWM delay from 100 μs to 50 μs	No substantial improvement
Added a 3 kHz low-pass filter to the voltage measurement path	Limited improvement
Used Half Bridge modules in Sub-cycle average mode	Smooth waveforms, but the post-disturbance oscillation characteristics changed

I also replaced the variable grid-inductance implementation with a fixed physical 2 mH grid in a separate diagnostic model. The ripple remained at a 10 μs fixed step size and was significantly reduced at 2 μs.

This indicates that the variable-inductance implementation is not necessary for the ripple to occur.

4. Real-Time Computational Limitations

When the RT-BOX 1 base step size was reduced to 5 μs, the application encountered consecutive overruns and was terminated.

One reported execution time was approximately 7.16 μs, exceeding the permitted 5 μs interval.

At a 10 μs base step size, the model can run, but occasional overruns have also been recorded, with some execution times exceeding 14 μs.

Therefore, directly reducing the CPU base step size to 2 μs does not appear feasible with the current model implementation.

5. Technical Questions

I would greatly appreciate your guidance on the following questions:

1. Is there a recommended approach for accurately simulating a 10 kHz PWM-controlled three-phase LCL inverter on RT-BOX 1 when the CPU base step size is limited to approximately 10 μs?

2. Is it possible to improve the switching-event time resolution using RT-BOX 1 hardware resources without requiring additional external PWM loopback wiring?

3. Could the periodic ripple around 1 kHz be caused by switching-event quantization exciting the LCL resonance, and are there recommended methods to reduce such numerical excitation?

4. Is there an optimized real-time implementation that retains the relevant switching and control-delay dynamics while reducing the computational burden?

5. Would you recommend any specific discretization method, power module configuration, or code-generation optimization for this application?

6. If a Sub-cycle average model is recommended, how can the original PWM timing and 100 μs control delay be represented accurately so that the stability characteristics remain consistent with the high-accuracy switched model?

6. Experimental Constraints

For this research, it is essential to preserve the original PR controller parameters, PWM switching frequency, control delay, and electrical parameters because the results will be compared with another control strategy under identical operating conditions.

In addition, the experiment must be performed entirely within RT-BOX 1, without external PWM loopback wiring. Only four analog output channels are used for oscilloscope measurements.

The intended experimental outcome is a smooth and stable three-phase voltage waveform at 2 mH, followed by a clear oscillatory response when the external grid inductance increases to 5 mH.

I can provide the complete PLECS model, offline simulation results, oscilloscope screenshots, FFT results, and RT-BOX diagnostic logs for further investigation.

the complete PLECS model

offline simulation results

oscilloscope screenshots

FFT Spectrum Before the Step Change at a 10 μs Time Step

FFT Spectrum Before the Step Change at a 2 μs Time Step

RT-BOX diagnostic logs

Thank you very much for your time and assistance. I would greatly appreciate any recommendations regarding a suitable real-time implementation.

[Bryan_Lieblick]

The first item to tackle is how you have implemented your PWM. You are generating the triangular wave explicitly in your model. With a fixed-step solver (both offline or on the RT Box CPU) the PWM duty cycles are then quantized to Tpwm/Tstep+1 which for 10 kHz PWM and 10 usec step is only 11 different duty cycles. This will lead to artifacts in your model. The PWM Out component from the RT Box library uses a clock on the FPGA which is 133 MHz for the RT Box 1 with is more than 13k different duty cycles.

Next, you are directly connecting boolean signals to the gate signal inputs of the switches. You had to insert data conversion blocks to bypass warning/errors explicitly telling you not do use this approach. This prevents use of a technique called sub-cycle averaging that enhances the accuracy of the PWM sensing and improves model accuracy.

The solution is to use the technique used in all of the RT Box Demo Models:

1. Replace the triangular wave generation with PWM Out blocks
2. Use PWM Capture block to sense the PWM inputs generated by the PWM Out blocks and connect directly to the switches (you can use simple Signal Switches or arithmetic for CPU based simulations, but you need to understand how sub-cycle averaging works. Do not boolean logic).
3. Loop the signals from the RT Box Digital Out to the Digital In blocks.

The relevant theory is also covered in the RT Box Tutorials In particular the “Introduction” (Section 6 in particular) and “Timing and Step-Size Selection”.

If you do not have access to a cable to loop the signals back from the Digital Out to the Digital In, you can also simulate this system as an average model by directly connecting the duty cycle m signals to the gates of your switches (m to upper and 1-m to lower, where m is from [0,1])

[runxinYan]

Thank you very much for your detailed explanation. Your comments have helped me better understand the limitations of my current PWM implementation.

I understand that the explicit triangular carrier comparison and Boolean gate signals may introduce duty-cycle quantization and prevent the use of sub-cycle averaging.

However, my current experimental setup does not permit additional physical connections between the RT-BOX digital output and digital input ports.

I have previously tested the Half Bridge modules in Sub-cycle average mode by directly applying duty-cycle reference signals. Although this significantly improved the voltage waveforms before the grid-inductance step, the oscillatory response after the step was different from that of the original high-accuracy switched model.

This is particularly important because my research focuses on stability analysis. The system should remain stable when the external grid inductance is 2 mH and exhibit an oscillation around 800 Hz when it increases to 5 mH.

The original PWM implementation also includes a 100 μs delay.

Could you please advise on the following points?

1. When directly applying duty-cycle signals to the Half Bridge modules in Sub-cycle average mode, how should the original PWM sampling behavior and 100 μs delay be represented?

2. Is the direct duty-cycle average model expected to reproduce the same small-signal stability characteristics as the original switched model, particularly near an LCL resonance?

3. Is there any alternative supported approach that provides sub-cycle PWM accuracy entirely within RT-BOX 1, without external digital loopback wiring?

My goal is to preserve the original control parameters and stability characteristics while improving the real-time simulation accuracy.

Thank you again for your assistance.

[Bryan_Lieblick]

1. When directly applying duty-cycle signals to the Half Bridge modules in Sub-cycle average mode, how should the original PWM sampling behavior and 100 μs delay be represented?

You can use a regular delay block at the duty cycle input to the modulator.

2. Is the direct duty-cycle average model expected to reproduce the same small-signal stability characteristics as the original switched model, particularly near an LCL resonance?

Depends how close the LCL resonances are to the PWM frequency. Worth doing a sanity check offline.

3. Is there any alternative supported approach that provides sub-cycle PWM accuracy entirely within RT-BOX 1, without external digital loopback wiring?

No, the sub-cycle averaging approach requires an electrical connection to the digital input signal.

Right now you are limiting the accuracy of the model by using the fixed step solver of the RT Box and then further limiting yourself by not using the built-in-methods to improve the simulation accuracy.

There is a larger discussion here about what is the overall goal of your experimental setup. You’re using the RT Box to interface your simulation with the real world, but right now it’s just connected to a bunch of Analog Out block. Will the outputs be analyzed in some way or act upon the circuit in response to the stimulus? A bit more information on your goals and desired setup would be helpful.

[runxinYan]

Hi Bryan,

Thank you so much for your detailed explanations and valuable suggestions!

With your help, I was able to identify the issues in my original PWM implementation and better understand the importance of sub-cycle averaging and proper delay modeling.

Following your advice, I modified the average model and used a Transport Delay block to represent the original 100 μs delay. The simulation now produces the expected results, and the issue I was struggling with has finally been resolved.

I really appreciate your patience and the time you spent helping me troubleshoot this problem. Your guidance has been extremely helpful to my research.

Thank you again for your support!

[Bryan_Lieblick]

Great to hear that was helpful and you are able to move forward with your research!