There’s not enough information to debug your model. I cannot see a ZOH in any of your screenshots. Is one missing? How does the PFC PLL on vg_sen relate to the DAB current imbalance?
I will note that the PLL implementation can be sensitive to a DC offset, but it looks like you’re directly measuring vg_sen from an ideal AC source.
i doubted it, which updates the phase shift twice per cycle. coz i measured the phase shift value, it didn’t balance during the positive and negative parts.