Thanks for the detailed description and model files.
1. CHB_PWM_option1 – PWM synchronization using the standard PWM blocks
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The relative phase between Phase A and Phase B keeps drifting when I was running the real-time of HIL+DSP operation modes.
This is to be expected. They are two separate DSPs with two different clocks that will naturally drift from each other.
I’ll also point out that you’ll likely encounter another synchronization related issue (if you haven’t already noted this). The sine generators for the duty cycle inputs are independently generated on each MCU. These also will drift over time and either need to come from a common source or be synchronized in some way.
After reading the related thread and found which can be alternatively use the PWM variable blocksets.
Yes, the more advanced PWM block is a workaround for your case.
For future users, I’ll also point out that the unique grouping here of 3 PWM generators sync’d is due to the specifics of the 28379D target, as explained in this forum post. You could group all PWMs into a common block for other targets.
2. CHB_PWM_option2 – PWM synchronization using PWM Variable blocks
However, after applying the same PWM phase settings, the resulting Phase A waveform is different from the waveform obtained with CHB_PWM_option1.
In your offline simulation you swapped the two PWM ports. “PWM (Variable)1” and “PWM (Variable)” are fed into the incorrect multiplexer inputs. Perhaps more descriptive names would help. Switching those fixed the issue in the offline simulation.
In the HIL implementation you are using a RT Box digital outputs (DO-8 and DO-9) that don’t map to a GPIO on the 28379D. You might be using fly wires since you’re connecting two boards to synchronization signals coming from 1x RT Box. For phase A I changed the pin assignment to DO-2 and GPIO 67 and it worked fine and matched the original implementation.
I also noted that you can have a more efficient real-time implementation by using the “Number of cells” setting with the “Full Bridges (Series Connected)” component rather than having two separate full-bridges.
Also, the effective output frequency is 40 kHz which is high relative to the CPU time step you chose at 5 usec (Tpwm/Ts_rtbox= 5). This results in a notable distortion near the current zero crossing. In my testing the step size can be decreased to 2 usec on the CPU (Tpwm/Ts_rtbox= 12.5) or even better set the system to use the FlexArray for a 154 nsec step size (Tpwm/Ts_rtbox= 162).
You can see the changes in the attached model. Note I didn’t make any modifications to the B_phase subsystems. CHB_PWM_OPTION2_BL.plecs (283.1 KB)