Your overall approach works fine but there are a few details that will cause your model to not work in hardware implementation.
- The 28379D has certain restrictions on how PWMs can be synchronized. See Figure 15-7 from the 2837xD Technical Reference Manual. PWM’s must be synchronized in groups of 3. In your original model you were trying to synchronize ePWM3 via a synchronization input, which it does not have. Only ePWM1, ePWM4, ePWM7, etc. have these synchronization inputs. I modified your model to have the synchronization chain set appropriately. One note is that there is a 2 ePWM clock delay between synchronized groups. You can correct for that by having a “dummy” PWM trigger the other two PWMs that will connect to your outputs. However, in that case you still are restricted by the IO capabilities of this target hardware and would have to do a bit more work to remap the RT Box inputs.
- You have resistors in series with your voltage sources which is not allowed for the sub-cycle average switch models. The DC port must be across an ideal voltage source or capacitor.
- The effective switching frequency is 60 kHz and you are using an RT Box 1 with a 5 usec step size. This is only 3.3 model steps per period on the RT Box, so the real-time performance will be poor. The results are much better with the FlexArray solver of the RT Box 2/3/4 as the step size is 147 nsec vs. 5 usec on the CPU in your model. However, you can use a purely resistive load for your testing purposes where the results are better.
Here is the modified model: 3H_c2000_openloop_BL.plecs
