Hello,
I am currently running an inverter simulation in PLECS using SiC MOSFETs, and I have a question about the reverse conduction behavior and conduction loss/current sharing model.
In my understanding, during the commutation interval when the bottom switch is conducting current and the top switch is turned on, the current in the bottom device should, in principle, be shared between the MOSFET channel (third-quadrant conduction) and the body diode. I would expect this current sharing to be determined by the on-state characteristics in the thermal model, such as the Ron / Von data, rather than being forced entirely into one path.
However, in my simulation I see the following:
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If I do not apply turn-on delay (dead time), then essentially no current flows through the body diode.
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If I do apply turn-on delay, then the current appears to split exactly 1:1 between the MOSFET channel and the body diode.
This behavior seems inconsistent with what I would physically expect. I would have expected the current sharing to depend on the conduction characteristics of the channel and diode, not simply on whether dead time is applied or not, and certainly not to split equally unless the device model explicitly enforces that.
Could you please explain why PLECS behaves this way?
Also, what is the correct way to model this so that the reverse conduction current sharing and conduction loss are represented properly for a SiC MOSFET in an inverter leg?
Thanks,