In a code generation subsystem, I have two CPU tasks: CPU1 executes at a rate of 40 kHz, and CPU2 executes at 10 kHz. During simulation, in an enabled subsystem of CPU2, an input signal, when viewed with an oscilloscope, has a discretization frequency of 10 kHz. However, once this signal enters the enabled subsystem, its discretization frequency becomes 40 kHz when viewed with the oscilloscope. What is the reason for this? How can I ensure that all signals in the task executed by CPU2 at a frequency of 10 kHz have a discretization frequency of 10 kHz?
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