I am looking for a recommended workflow or example model to run a Current Source Inverter (CSI) simulation on the RTBox for a Hardware-in-the-Loop (HIL) application. The setup uses GaN Bidirectional Switches (BDS).
Because of the CSI topology, controlling and observing the overlap time (make-before-break) with sub-microsecond precision is critical to prevent inductive overvoltages.
Does the RTBox framework support a specialized sub-microsecond or “nano-step” simulation mode capable of capturing these microscopic logic and commutation behaviors accurately in real-time? What is the minimum achievable step size or PWM resolution for this specific use case on the RTBox?
There isn’t a built in library component for current source inverter, but two approaches come to mind:
Nanostep Component Modification
The 3x1 Matrix CLLLC Converter could be manipulated to represent your topology. This is likely a better fit for the GaN BDS devices and uses the Nanostep solver so the PWM sampling and make-or-break detection happens at 4 nsec.
Some recommended settings:
Set the full bridge gate signals as constants
Set primary leakage inductance and primary winding resistance to your inductive link values and magnetizing inductance to “inf” (you can enter the string directly in the mask).
Set Include primary capacitor, Include secondary inductance , and Include secondary capacitor to “no”
There is the a “Current Source Inverter” in the TI C2000 Target Support Package demos that shows a custom implementation of a CSI block. The CSI arrangment is the IGBT with series Diode instead of GaN BDS. It uses sub-cycle averaging techniques with a CPU based solver. On the RT Box 2, 3, and 4 this means the PWMs are sampled every 3.3 nanoseconds, but the converter states are updated at the CPU step (e.g. 2.5 usec in the aforementioned demo). At higher switching frequencies (or smaller overlap windows) this may become limiting.
