Overview
Advances in wide-bandgap devices allow DC/DC converters to switch at much higher frequencies than with silicon devices. These converters are a challenge for hardware-in-the-loop (HIL) testing, because the HIL simulator must calculate each step in real time and still resolve each switching period with enough samples. The figure shows the number of samples per switching period over the switching frequency for five HIL solver step sizes. For each step size, the number of samples drops in proportion to the switching frequency. At 100 kHz, for example, a step size of 4 ns gives 2500 samples per period, and a step size of 1 µs gives only 10.
Figure: Samples per switching period over the switching frequency for HIL solver step sizes from 4 ns to 1 µs.
HIL validation of high-frequency converters therefore needs a solver with a very small step size, or other techniques that keep enough samples per switching period. The RT Box offers two FPGA-based solvers. The NanoStep solver solves a wide range of topologies at a step size of 4 ns. For topologies that the NanoStep solver does not support, the FlexArray solver reaches step sizes between 50 ns and 200 ns, depending on the circuit complexity. For converters that switch at several hundred kilohertz, this can still give too few samples per period.
This article uses a three-phase LLC converter as an example. Three-phase LLC converters are used in high-power applications from EV charging to data center power supplies. Compared with a single-phase LLC converter, the three-phase converter has a lower current ripple and smaller components, and its control is simple to implement [1]. Direct frequency control regulates the output current, as in the single-phase converter.
The three legs of the converter operate with a 120° phase shift, which cancels much of the current ripple. Because the three half-bridges switch at different times, the converter has six switching events per period, and the solver must resolve the time between them. To get this resolution with the FlexArray solver, the model uses time scaling: the RT Box and the controller both run slower than real time, in lock-step. For this example, the FlexArray solver reaches 139 ns, and a scale factor of 1/10 reduces the effective step size to 13.9 ns. This cuts the deviation of the RMS currents from a continuous-domain reference from up to 13.8 % to below 1 %. Time scaling makes HIL testing possible when the solver cannot reach the required step size in real time. The cost is that the model no longer runs in true real time.
The example is an 11 kW converter. The controller runs on a TI F29H850TU9 MCU with code generated by the PLECS TI C2000 Target Support Package (TSP), and the plant runs on the PLECS RT Box 2.
Model
The top-level schematic has two subsystems: “Plant” and “Controller”. Both subsystems are enabled for code generation from the Edit + Subsystem + Execution settings… menu. The PLECS Coder generates the code for the RT Box from “Plant” and the code for the MCU from “Controller”.
Power Circuit
The plant is a three-phase LLC converter. The power stage parameters are taken from [2]:
| Parameter | Value |
|---|---|
| Output power | 11 kW |
| Input voltage | 400 V |
| Battery voltage | 400 V (0.1 Ω series resistance) |
| Resonant capacitor C_r | 127 nF per leg |
| Resonant inductance L_r | 20 µH per leg |
| Magnetizing inductance L_m | 115 µH |
| Turns ratio | 14:15 |
| Resonant frequency f_r | 100 kHz |
| Switching frequency range | 75 kHz to 150 kHz (0.75 f_r to 1.5 f_r) |
| Deadtime | 200 ns |
| Output capacitor | 4.7 µF |
The table gives the values of the real converter. The model scales the values at initialization, as described in Time-Scaling Concepts.
The input is an ideal DC voltage source. The battery is modeled as an ideal DC voltage source with a series resistance. The primary side is a three-phase voltage source inverter. Each half-bridge connects to its own resonant inductor, resonant capacitor and transformer leg. Each transformer leg has its own magnetizing inductance. The secondary side is a three-phase diode bridge rectifier. The primary and the secondary windings are both connected in star configuration. The phase legs are implemented using the physical domain vectorized modeling technique.
Theory of operation
As in the single-phase LLC converter, each half-bridge switches at a duty cycle of 50 %, and the switching frequency sets the converter gain. The three half-bridges are shifted by 120°. In an ideal converter, this phase shift cancels part of the ripple at the input and at the output, so smaller filter components can be utilized.
RT Box configuration
The plant runs on the RT Box and connects to the MCU through the RT Box Nucleo-LaunchPad Interface board.
The three-phase inverter and the three-phase diode rectifier are modeled with power modules from the PLECS library. Both power modules use the sub-cycle average configuration, which supports code generation for the RT Box. With these power modules, and with the FlexArray solver selected in the Model Settings block, the RT Box solves the electrical circuit with a step size of 139 ns.
The RT Box sends one measurement to the MCU: the battery current. A first-order low-pass filter models the battery current sensor. The filter is modeled with a simple Transfer Function block. Because of this block, the filtered current is calculated by the CPU solver, which has a step size of 2.5 µs, and not by the FlexArray solver. This is acceptable, because the bandwidth of the output current controller is low. The generated code transfers the current from the FlexArray solver to the CPU solver automatically, so no extra blocks are needed in the model. At each CPU step, the RT Box scales the filtered current and sends it to the MCU through an analog output.
Controls
The controller regulates the output current with direct frequency control. The ADC measures the output current i_\mathrm{batt}, which charges the battery, and a PI controller changes the switching frequency to regulate it to the reference i_\mathrm{batt,ref}.
The interleaved legs and the high switching frequency keep the output current ripple small, and the current sensor filters it further. The control therefore needs neither its sampling nor its control task to be synchronized to the PWM. A PWM-triggered task would run at a rate that changes with the switching frequency, and so would the sample time of the PI controller. A fixed-rate task avoids this. In this model, a Timer block triggers the control task.
The gain of an LLC converter decreases when the switching frequency increases. To increase the output current, the controller must decrease the switching frequency. For this reason, the error is calculated as:
The PI controller does not calculate the normalized switching frequency f_n = f_\mathrm{sw}/f_r directly. It calculates an offset u from the maximum normalized frequency f_{n,\max}:
With this structure, the converter always starts at the maximum switching frequency when the PI controller is reset to 0. This is the operating point with the lowest gain, so the output current starts low and rises as the controller decreases the frequency.
The output of the PI controller is limited to the range from f_{n,\min} - f_{n,\max} to 0. The PI controller has anti-windup, so the integrator stops integrating while the output is at a limit. With f_{n,\min} = 0.75 and f_{n,\max} = 1.5, the output range is −0.75 to 0. The switching frequency therefore stays between 0.75 f_r and 1.5 f_r, which is 75 kHz to 150 kHz.
The compensator is tuned with the frequency response of the converter at maximum load. The compensator zero is at 500 Hz, and the open loop has a crossover frequency of 581 Hz, with a phase margin above 90° and a gain margin above 11 dB. With time scaling, all of these frequencies are multiplied by the scale factor, as described in Time-Scaling Concepts.
Time-Scaling Concepts
Real-time simulation is a trade-off between model complexity and model fidelity. A more complex model takes longer to calculate. A higher fidelity can require a very small step size, which leaves less time to calculate each step. At some point, the calculation time of a step exceeds the step size, and the model can no longer run in real time.
Time scaling is one way to overcome this limit. The plant model on the HIL simulator and the embedded controller both run slower than real time, in lock-step. If the model runs at 1/10 of real time, an event that takes 1 s in the real system takes 10 s in the time-scaled model. With the parameters scaled correctly, the model keeps the dynamics of the real system, apart from the discretization error, and the HIL simulator has more time to calculate each step.
The time-scaling factor K_\mathrm{timeScale} is smaller than 1 for a model that runs slower than real time. In the model initialization commands, this factor is the variable K_timeScale. The plant is scaled as follows:
- All inductances, capacitances and time constants are divided by K_\mathrm{timeScale}. This changes all L/R and RC time constants of the circuit by the same factor.
- All frequencies are multiplied by K_\mathrm{timeScale}.
- Voltages, currents, resistances and power do not change.
The HIL simulator still calculates the model with its usual step size T_\mathrm{s,HIL}. Because the scaled plant runs slower than the real system, one HIL step represents a shorter time in the real system. This effective step size is:
For example, with K_\mathrm{timeScale} = 1/10 and a HIL step size of 139 ns, each step represents 13.9 ns in the real system.
Selecting the scale factor
A smaller scale factor gives a smaller effective step size and a more accurate plant. The slow-down has a limit, however: the MCU peripherals are still clocked by the MCU oscillator, for example at 100 MHz. With too much slow-down, the scaled timing exceeds what the peripherals can handle. For example, the scaled PWM period no longer fits in the range of the PWM counter. The scale factor must therefore balance the accuracy of the plant against the capabilities of the peripherals. Offline simulations in PLECS can be utilized to find this factor:
- Determine the step size that the FlexArray solver reaches for the circuit on the RT Box.
- Simulate the plant in the continuous domain. This simulation is the reference.
- Simulate the plant discretized with the FlexArray step size, and compare the quantities of interest with the reference, for example the steady-state RMS values of the converter currents. If the deviations are within the tolerance, the model runs in real time and needs no time scaling.
- Otherwise, select a scale factor K_\mathrm{timeScale} = 1/n with an integer n. The effective step size is then K_\mathrm{timeScale} times the FlexArray step size.
- Simulate the plant discretized with the effective step size, and compare it with the reference again. Repeat steps 4 and 5 with a larger n until the deviations are within the tolerance.
- Check that the scaled rates of the control task, the PWM and the ADC are within the capabilities of the MCU peripherals. If they are not, the accuracy requirement and the peripheral limits cannot both be met with time scaling alone.
For this model, the FlexArray solver reaches a step size of 139 ns. All comparisons are made at full load, 11 kW. The table lists the deviation of the steady-state RMS values from the continuous-domain reference, calculated as:
For the three legs, the table gives the range of the deviations.
| Quantity | 139 ns | 13.9 ns |
|---|---|---|
| Magnetizing current | 13.4 % to 13.8 % | 0.6 % |
| Resonant leg current | 3.8 % to 4.1 % | 0.5 % to 0.6 % |
| Output current | 0.7 % | below 0.1 % |
At 139 ns, the RMS value of the output current is close to the reference, but the magnetizing currents deviate by about 14 % and the resonant leg currents by about 4 %. The waveforms also differ: the peak values of the resonant leg currents rise from 31.4 A to about 36 A, and the output current ripples between 17.3 A and 34.5 A in steady state instead of between 24.4 A and 29.0 A.
As a first candidate, the model uses a scale factor of K_\mathrm{timeScale} = 1/10. The initialization commands set it in the variable K_timeScale. The effective step size is:
At this step size, the steady-state RMS values of all three currents are within 1 % of the reference, so no further iteration is needed.
With K_\mathrm{timeScale} = 1/10, the controller runs 10 times slower than on the real converter. The control task runs at 5 kHz instead of 50 kHz, and the switching frequency is 7.5 kHz to 15 kHz instead of 75 kHz to 150 kHz. The PWM runs from a 100 MHz clock in up-count mode, so the period at the lowest scaled switching frequency of 7.5 kHz is about 13,300 counts. This fits in the 16-bit PWM counter, which limits the switching frequency to at least 1.53 kHz, or a scale factor of about 1/49 for this converter. A scale factor of 1/10 therefore meets both the accuracy and the peripheral requirements.
Scaling the controller
Time scaling also requires changes to the controller, because the controller must run at the scaled rate. The table lists the parameters that change in this model, with their real values and their scaled values for K_\mathrm{timeScale} = 1/10:
| Parameter | Variable | Scaling | Real value | Scaled value |
|---|---|---|---|---|
| Switching frequency | from f_r | \times K_\mathrm{timeScale} | 75 kHz to 150 kHz | 7.5 kHz to 15 kHz |
| Control task rate | freq_isr |
\times K_\mathrm{timeScale} | 50 kHz | 5 kHz |
| Deadtime | T_dt |
\div K_\mathrm{timeScale} | 200 ns | 2 µs |
| Current sensor filter pole | i_batt_sense.filterPole |
\times K_\mathrm{timeScale} (via freq_isr) |
5 kHz | 500 Hz |
| Compensator zero f_z | ibattCtrl.fz |
\times K_\mathrm{timeScale} | 500 Hz | 50 Hz |
| Compensator gain K | ibattCtrl.K |
\times K_\mathrm{timeScale} | 5 | 0.5 |
| Crossover frequency | (result) | \times K_\mathrm{timeScale} | 581 Hz | 58.1 Hz |
The switching frequency limits are calculated from the scaled resonant frequency, so the PWM carrier frequency scales automatically. The simulation time and the analysis settings are scaled as well.
The general rule is that every controller parameter with a unit of time or frequency must be scaled. Parameters without a unit, and parameters defined per sample or per switching period, do not change.
The output current controller is a discrete PI controller. Its gains are entered in continuous-time form: the proportional gain K_p has no unit, and the integral gain K_i has the unit 1/s. The block integrates the error with the sample time of the control task. Time scaling makes this sample time 1/K_\mathrm{timeScale} = 10 times longer. During one control task period, the plant changes by the same amount as in the real system. With an unchanged K_i, however, the integrator would add 10 times more per control task period. The integral action would be 10 times too strong, and the loop would become unstable. K_i must therefore be multiplied by K_\mathrm{timeScale}, and K_p does not change.
The model sets the gains from the compensator gain K and the zero frequency f_z. Here, K is the gain that defines the compensator, not the proportional gain K_p:
Both K and f_z are multiplied by K_\mathrm{timeScale}. The factors cancel in K_p, so only K_i is scaled.
When the controller runs with the real power stage, the scale factor is set to 1, and the controller changes have no effect.
Because the controller runs at the scaled rate, the HIL test does not verify the real-time behavior of the controller. Scope and Limitations lists what the test verifies and what it does not.
HIL Test Setup
The HIL setup uses a PLECS RT Box 2 to emulate the three-phase LLC power stage with time scaling. The controller runs on a TI F29H850TU9 LaunchPad. The RT Box and the LaunchPad are connected through the RT Box Nucleo-LaunchPad Interface board.
HIL Results
The figure compares the HIL test with an offline simulation of the same time-scaled model at full load in steady state. The solid lines are captured from the RT Box in external mode, and the dashed lines are from the offline simulation. The time axis is the wall-clock time of the time-scaled model. Without time scaling, the same interval would contain 10 times as many switching periods.
Figure: Resonant leg currents, magnetizing currents and output current in steady state. Solid: HIL test. Dashed: offline simulation. Both with time scaling.
External mode captures the signals of the RT Box at the CPU step size of 2.5 µs, so the HIL waveforms are stepped. At the operating point shown, this gives about 37 samples per switching period. The steps come from the capture, not from the plant, which the FlexArray solver calculates at 139 ns.
The resonant leg currents, the magnetizing currents and the output current of the HIL test follow the offline simulation closely, including the phase shift between the legs and the output current ripple.
The table lists the deviation of the steady-state RMS values of the HIL test from the offline simulation. The deviation is calculated as in Selecting the scale factor, with the offline simulation as the reference. For the three legs, the table gives the range of the deviations.
| Quantity | Deviation |
|---|---|
| Resonant leg current | 0.2 % to 0.4 % |
| Magnetizing current | below 0.1 % |
| Output current | 0.3 % |
The RT Box therefore reproduces the time-scaled offline model for the steady-state currents at full load.
Scope and Limitations
The time-scaled HIL test verifies the controller functionally: the control algorithm, the measurement scaling and ADC configuration, the PWM configuration and phase shifts, and the closed-loop interaction with the plant. Because the controller runs at the scaled rate, the test does not verify timing and resolution at the real rate:
- The CPU load of the control task at the real rate.
- The PWM resolution at the real switching frequency.
These items must be verified with the controller running at the real rate, for example with the real power stage.
The model does not include the following:
- Burst mode at light load.
- Synchronous rectification on the secondary side.
Conclusion
High switching frequencies leave few solver steps per switching period, and this makes HIL testing of wide-bandgap DC/DC converters difficult. This article showed how to test such a converter on the RT Box, using an 11 kW three-phase LLC converter as the example. The FlexArray solver with sub-cycle average power modules solves the circuit at 139 ns. Time scaling with a factor of 1/10 brings the effective step size to 13.9 ns.
The scale factor is selected with offline simulations: the discretized plant is compared with a continuous-domain reference, and a factor that meets the accuracy tolerance is used, within the limits of the MCU peripherals. In this example, the deviations of the RMS currents drop from up to 13.8 % at 139 ns to below 1 % at 13.9 ns. Once the factor is set, every plant and controller parameter with a unit of time or frequency is scaled with it, and the model keeps the dynamics of the real system, apart from the discretization error. The same controller model generates the code for the TI F29H850TU9 MCU through the TI C2000 TSP, and setting the scale factor to 1 returns the controller to its real-time parameters. In the HIL test, the RMS currents agree with the time-scaled offline simulation within 0.4 %. The time-scaled HIL test verifies the control algorithm and the peripheral configuration, but not the real-time behavior of the controller.
Requirements
- PLECS Standalone 5.0 or newer
- RT Box Software 4.0 or newer
- TI C2000 TSP 2.3 or newer
References
[1] Texas Instruments. “Implement Three-Phase Interleaved LLC on C2000 Type-4 PWM.” Application Note SPRAD15, Mar. 2022. https://www.ti.com/lit/pdf/sprad15
[2] Frolov, Filipp, Pavel Skarolek, and Jiri Lettl. “Online RMS-Based Current-Balancing Algorithm for Three-Phase LLC Resonant Converters.” Electronics, vol. 15, no. 7, 2026, article 1417. https://doi.org/10.3390/electronics15071417
Downloads
| File | Description |
|---|---|
| three_phase_LLC.plecs | Real-time simulation of a three-phase LLC converter using time scaling techniques. |