Predicting the delay and magnitude attenuation introduced by a PWM modulator is one of the less intuitive steps in designing a digital control loop. Get it wrong and the loop behaves differently in hardware than expected. This article derives the analytical small-signal frequency response for three common carrier shapes and uses PLECS to measure it directly, showing that simulation results match theory closely, even for complex PWM-driven circuits.
Naturally Sampled PWM
The image below shows a PLECS block diagram of a naturally sampled PWM generator, which corresponds to the classical analog implementation found in traditional analog controllers and PWM modulator ICs.
In this implementation, a voltage representing the duty command (reference) is compared against a carrier waveform voltage using a comparator: the output goes high whenever the reference exceeds the carrier, producing the PWM waveform shown above.
Here, a symmetrical (triangular) carrier ranging from 0 to 1 at 10 kHz is used. Sawtooth carriers with either a rising or falling slope are also commonly employed, each resulting in different PWM pulse positioning within the switching period.
Because the duty command is continuous, it intersects the carrier at its natural crossing points. This introduces no delay and no magnitude attenuation. This makes naturally sampled PWM the theoretical benchmark for the regularly sampled modulators examined in this article.
Regularly Sampled PWM
The next image depicts a regularly sampled PWM generator (also called uniformly sampled PWM), representative of how PWM is implemented in a digital control loop.
Unlike the naturally sampled case, the reference signal is first passed through a Zero-Order Hold (ZOH) with a sampling period of T_s, typically equal to the switching period, before being compared against the carrier. This models the sample-and-hold behavior inherent to digital controllers, where the duty cycle command is computed once per switching period and held constant until the next sample. This accurately models a real digitally controlled power converter.
It is also possible for the digital control loop to run at a lower (or even higher) frequency than the PWM switching frequency, in which case the ZOH sample time corresponds to the control loop sample time rather than the switching period.
Asymmetrical Carriers
With an asymmetrical (sawtooth) carrier, the duty cycle is latched exactly once per
period — at the overflow/underflow event where the carrier resets. This single latch
point is marked DUTY LOAD in the timing diagrams below.
-
Trailing-Edge (TE): The carrier ramps upward and resets at the end of the
period. The new duty value is latched at the reset, so the rising edge of the PWM
pulse is fixed at the start of the next period and the falling (trailing) edge moves
with the duty cycle. -
Leading-Edge (LE): The carrier ramps downward and resets at the end of the
period. The duty is again latched once at the reset, but now the falling edge of the
pulse is fixed at the end of the period and the rising (leading) edge moves with the
duty cycle.
Symmetrical Carriers
With a symmetrical carrier, the duty cycle is latched at the carrier
peak or zero, which each occur once per period. The instant of latching determines which
edge of the PWM pulse is modulated first after the latch, giving rise to two variants:
-
Symmetrical TE-LE: The carrier rises from zero, crossing the duty threshold
to produce the trailing (TE) edge of the pulse first, before falling again to produce
the leading (LE) edge. -
Symmetrical LE-TE: The carrier shape is inverted relative to TE-LE, so the
leading (LE) edge is produced before the trailing (TE) edge within the switching
period.
In both symmetrical variants, the pulse is centred within the switching period,
and the average transport delay is independent of the duty cycle.
Small-Signal Frequency Response of Regularly Sampled PWM Modulators
To understand how regular sampling introduces delay, consider what happens when
the duty cycle command is perturbed by a small amount \hat{d}. Because the duty
value is held constant by the ZOH until the next latch point, the perturbation
cannot affect the PWM output until the carrier next crosses the updated threshold.
That crossing corresponds to a modulated edge of the pulse.
Referring back to the timing diagrams in the previous section, it is clear which
edges are modulated in each case. Because the duty value is held constant by the ZOH until the next latch, a perturbation \hat{d} can only shift the PWM output at the instant the carrier crosses the updated threshold. That instant is set by the nominal position of the modulated edge within the switching period:
- Asymmetrical Trailing-Edge: The trailing edge sits at D \cdot T_\text{PWM} after the latch, so the transport delay is D \cdot T_\text{PWM}.
- Asymmetrical Leading-Edge: The leading edge sits at (1-D) \cdot T_\text{PWM} after the latch, giving a transport delay of (1-D) \cdot T_\text{PWM}.
- Symmetrical: Both a trailing edge and a leading edge are modulated within each switching period. The perturbation shifts these two edges by equal and opposite amounts, so the effective delay is the average of the two, which is always T_\text{PWM}/2 regardless of duty cycle.
This geometric reasoning gives an intuitive picture of the delay, but does not
immediately account for the attenuation in the symmetrical case. For a rigorous
derivation that includes both effects, the reader is referred to [1].
The result of [1] can be written in the following unified form:
| Modulator Type | Small-Signal Frequency Response | Transport Delay t_{DPWM} |
|---|---|---|
| Asymmetrical (sawtooth) | G_{PWM}(j\omega) = e^{-j\omega \tilde{D} T_{PWM}} | \tilde{D} T_{PWM} |
| Symmetrical (symmetrical) | G_{PWM}(j\omega) = \cos\!\left(\dfrac{\omega \tilde{D} T_{PWM}}{2}\right) e^{-j\omega \frac{T_{PWM}}{2}} | T_{PWM}/2 |
where \tilde{D} corresponds to:
| Modulator Type | \tilde{D} |
|---|---|
| Asymmetrical Trailing-Edge | D |
| Asymmetrical Leading-Edge | 1-D |
| Symmetrical TE-LE | 1-D |
| Symmetrical LE-TE | D |
The asymmetrical modulators therefore exhibit a pure, duty-cycle-dependent
transport delay with no magnitude attenuation. Since the trailing-edge delay is
D \cdot T_{PWM} and the leading-edge delay is (1-D) \cdot T_{PWM}, the
trailing-edge modulator offers lower delay for duty cycles below 50%, while the
leading-edge modulator becomes faster above 50%. The symmetrical modulator
represents a compromise: it trades the variable delay for a fixed T_{PWM}/2
regardless of duty cycle, at the cost of the frequency-dependent magnitude
attenuation represented by the cosine factor.
N-Cycle Symmetrical Modulator
In a digital control loop running at a sub-multiple of the PWM frequency, the same
duty value drives N consecutive PWM cycles before the next update, where
T_s = N \cdot T_{PWM}. For the symmetrical
modulator, the small-signal frequency response generalizes to:
| Modulator Type | Transfer Function |
|---|---|
| Symmetrical | G_{PWM,Sym}(j\omega) = \cos\!\left(\dfrac{\omega \tilde{D} T_{PWM}}{2}\right) e^{-j\omega T_{eff}} \cdot \dfrac{\sin(N\pi f T_{PWM})}{N\sin(\pi f T_{PWM})} |
where \tilde{D} is defined per modulator type as in the single-cycle case, the
effective delay is T_{eff} = T_s/2 (half the control loop sample period), and
the multi-cycle averaging term \frac{\sin(N\pi f T_{PWM})}{N\sin(\pi f T_{PWM})}
introduces a magnitude rolloff that goes to zero at f = 1/(N T_{PWM}).
For N=1, the expression reduces to the single-cycle result of [1], and
for N=2 the multi-cycle averaging term simplifies to \cos(\pi f T_{PWM}).
Measuring the PWM Transfer Function in PLECS
The frequency response of a regularly sampled PWM modulator can be measured directly in PLECS using the built-in Frequency Response Analysis tool. The image below shows the simulation setup: a small sinusoidal perturbation is superimposed on the DC operating point (duty cycle of 0.25) before being passed through the ZOH block, which models the sample-and-hold behavior of the digital controller. The comparator then generates the PWM output, and the Response block measures the output signal for the frequency analysis.
By sweeping the perturbation frequency and computing the ratio of the output response to the input perturbation, PLECS extracts the small-signal frequency response of the modulator directly from simulation, without requiring any analytical model.
The image above shows the resulting Bode plots for all three carrier shapes at a duty cycle of 0.25 and a switching frequency of 10 kHz. In the magnitude plot, the trailing-edge and leading-edge modulators both show a flat 0 dB response across the entire frequency range, while the symmetrical modulators exhibit a visible rolloff at higher frequencies, corresponding to the cosine attenuation term in their transfer functions. In the phase plot, the modulators diverge at higher frequencies, with the falling-edge modulator showing the largest phase lag at this operating point, consistent with its transport delay of (1-D)T_{PWM} = 0.75 \cdot T_{PWM}.
The table below compares the measured values from the PLECS simulation against the
analytical predictions at f \approx 4\,\mathrm{kHz} (= 0.4\,f_\mathrm{sw}),
a frequency high enough to clearly distinguish the three responses:
| Modulator | Predicted Magnitude | Measured Magnitude | Predicted Phase | Measured Phase |
|---|---|---|---|---|
| Trailing-Edge | 0.000\,\mathrm{dB} | -0.002\,\mathrm{dB} | -36.55° | -36.56° |
| Leading-Edge | 0.000\,\mathrm{dB} | -0.002\,\mathrm{dB} | -109.66° | -109.67° |
| Symmetrical TE-LE | -4.791\,\mathrm{dB} | -4.743\,\mathrm{dB} | -73.11° | -73.08° |
| Symmetrical LE-TE | −0.450\,\mathrm{dB} | −0.402\,\mathrm{dB} | -73.11° | -73.11° |
The agreement between simulation and theory is excellent across all three modulator
types.
A second example extends the measurement to a more realistic scenario, representative of a typical embedded control loop. The PLECS model superimposes a small-signal perturbation on a DC duty cycle of 0.25 and passes the sum through a ZOH with sample period T_s = 100\,\mu\text{s}. This models a digital controller that updates its duty command at 10 kHz — half the 20 kHz switching frequency — so N = 2 PWM cycles elapse between updates. A Pulse Delay of T_d = 25\,\mu\text{s} follows the ZOH, representing computational latency before the new duty value is loaded into the PWM compare register. The delayed command then drives a symmetrical triangular carrier (Min = 0, Max = 1, f_\text{pwm} = 20\,\text{kHz}, Delay = 25\,\mu\text{s}). The Response block records the comparator output for the frequency sweep.
The 25\,\mu\text{s} carrier delay shifts the triangular waveform so that its minimum (underflow) falls at t = 25\,\mu\text{s}. Combined with the Pulse Delay, the updated duty command arrives at the comparator exactly at carrier underflow, where the carrier is about to rise. The carrier therefore first crosses the duty threshold on its rising slope, producing the Trailing Edge (TE) of the output pulse, before crossing again on the falling slope to produce the Leading Edge (LE). This identifies the modulator as symmetrical TE-LE, for which the attenuation parameter is \tilde{D} = 1 - D = 0.75, and the effective transport delay is T_\text{eff} = T_s/2 + T_d = 75\,\mu\text{s}. With N = 2, the multi-cycle averaging term simplifies to \cos(\pi f T_\text{pwm}), giving the complete transfer function:
The Bode plot shows the analytical prediction as a solid line extended to the control-loop Nyquist frequency f_{Ny} = 1/(2T_s) = 5\,\text{kHz}, with PLECS simulation results overlaid as dots. The magnitude response is nearly flat at low frequencies (-0.17\,\text{dB} at 1 kHz) and rolls off as both cosine terms grow, reaching -4.41\,\text{dB} at 4.9 kHz and -4.61\,\text{dB} at the Nyquist limit. The phase is a straight line with slope -360° \times T_\text{eff} = -27\,°/\text{kHz}, the signature of a pure transport delay, accumulating -135° at Nyquist. Simulation and theory agree closely: the RMS magnitude error is 0.020 dB and the RMS phase error is 0.033° across all 100 measured frequencies. The maximum discrepancy is 0.12 dB and 0.2° near the upper end of the sweep, well within the accuracy of the time-domain frequency extraction method.
PLECS Library Components
The modulator blocks available in the PLECS component library directly implement the configurations analyzed in this article.
As shown in the images above, PLECS provides dedicated Sawtooth PWM and Symmetrical PWM blocks, each with configurable sampling parameters that correspond to the modulator types discussed here.
The Sawtooth PWM block allows selection of the ramp direction. A falling ramp corresponds to the trailing-edge modulator; a rising ramp corresponds to the leading-edge modulator. It also provides a Regular sampling configuration, which implements the sampling behavior modeled by the ZOH in this article.
The Symmetrical PWM block uses a symmetrical carrier and offers a Regular sampling mode with a single update at either the minimum or maximum of the carrier. Updating at the carrier minimum corresponds to loading the new duty value at the underflow event, which is the standard single-update symmetrical modulator with the T_{PWM}/2 transport delay.
For users targeting real MCU hardware, the PLECS Target Support Packages provide processor-specific PWM blocks that map directly onto the same modulator types.
The TI C2000 PWM block, for example, offers a choice between a sawtooth and a symmetrical carrier.
For the sawtooth carrier, the sequence parameter determines the pulse positioning: a positive sequence — where the active state begins at carrier underflow — corresponds to a leading-edge modulator, while a negative sequence corresponds to a trailing-edge modulator.
The symmetrical carrier produces a pulse centered around the carrier zero (positive sequence) or around the carrier peak (negative sequence). Depending on when the compare values are reloaded, it will behave as the symmetrical lead-trail or symmetrical trail-lead type.
Summary
The type of PWM carrier has a direct effect on the small-signal frequency response of the modulator. Sawtooth carriers introduce a pure transport delay that depends on the duty cycle, while the symmetrical carrier produces a fixed delay of half the switching period accompanied by a frequency-dependent magnitude attenuation. When the control loop runs at a sub-multiple of the switching frequency, an additional multi-cycle averaging effect further shapes the frequency response.
Whether working with a generic simulation model or targeting a specific MCU, PLECS gives you accurate frequency response measurements out of the box, so you can characterize your modulator, catch loop-stability issues early, and move forward with confidence in your simulation results.
References
[1] L. Corradini, D. Maksimovic, P. Mattavelli, and R. Zane, Digital Control of High-Frequency Switched-Mode Power Converters, IEEE Press, 2015 — Appendix C, eq. (C.31).