The parallel capacitance issue of the full-bridge LLC resonant converter model

I would like to know,in the NanoStep component library,for the Full-Bridge LLC Converter,how to add an additional capacitor in parallel.The main reason is to achieve zero-voltage turn-on(ZVS) in the Full-Bridge LLC Converter topology.

Hi Jin,

The Nanostep modules are not modifiable, as they are specifically constructed to run at 4 ns on the RT Box using the Nanostep solver.

If your goal is to model this behavior in offline simulation, you can create the LLC converter of interest using the MOSFET with Diode component and add the parasitic components across the FETs as needed. However, this level of customization is currently not feasible for HIL simulation using the Nanostep modules.

I think the key question is whether, in the HIL simulation, your intention is to do something with the node voltage on the microcontroller side, such as implementing an adaptive dead-time algorithm or something similar. A little more context would be helpful.