Hi Sanket,
The simulation step size is what governs the sampling rate your model actually experiences (1 sample/step). The 5 MSPS continuous ADC sampling gives you sub-step timing precision for selecting when within that step the one sample is taken. It does not increase the number of samples delivered per step.
The purpose of the 5 MSPS continuous sampling isn’t to deliver more samples per step to the model. It’s to let you precisely place the one sample you do get within the step. This is especially useful for synchronizing an ADC measurement with a specific instant relative to a PWM switching edge (via “Use PWM trigger port”), so you capture, e.g., the exact midpoint of a switching cycle rather than being limited to values available only at fixed simulation step boundaries.
If I select Global Settings, and depending on the Coder option settings, will all analog pins be sampled simultaneously at each simulation time step only once?
Yes. With “Global Setting” selected, every Analog In channel is sampled simultaneously, exactly once per simulation step, at the instant configured in the “Analog input sampling” field of the Coder Options dialog (General tab). Only that single value per channel is passed into the model for that step.
If I want to achieve a 5 MSPS sampling rate, should I select “Specify delay within simulation step” and set the delay to 0?
Yes, but the behavior may not be as you expect. Selecting “Specify delay within simulation step” switches the ADC into continuous sampling mode. The hardware ADC runs continuously at 5 MSPS in the background, for all channels, throughout the entire simulation step. However, only one of those continuously-acquired samples (or their interpolation) is ever transferred to the CPU/model per simulation step. The “Trigger delay(s)” field just controls which instant within the step that single transferred sample corresponds to. A delay of 0 means “take the sample as early as possible in the step,” not “take a new sample every 200 ns.”
However, I still observe a discretized waveform corresponding to the simulation step size of 50 µs.
Because regardless of how the ADC is configured, the simulation model itself only receives one new Analog In value per simulation step. Since your step size is 50 µs, the model (and the scope trace) can only ever update at that rate: 20 kSPS as seen by the simulation, even though the ADC hardware is physically sampling at 5 MSPS underneath.
In this configuration, when exactly is the 5 MSPS sampling rate activated?
It’s active continuously, in hardware, for the full duration of every simulation step, whenever continuous sampling mode is enabled (i.e., “Specify delay within simulation step” or “Use PWM trigger port”). It runs the whole time it’s just that only one of those fast samples per step is selected and handed off to the CPU.
Is the 5 MSPS sampling rate independent of the simulation step size, or does the simulation step size need to be configured differently to observe the actual sampling rate?
They’re two separate things:
- The 5 MSPS rate is the ADC’s physical acquisition rate and is independent of your simulation step size.
- The simulation step size determines how often your model executes. Only one of the ADC samples actually make it into your model/scope per step.
So increasing the effective sampling rate seen in your model requires reducing the simulation step size itself (down to what your real-time execution budget allows), not adjusting the trigger delay.
