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Welcome to PLECS User Forum! :wave:
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0
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214
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July 4, 2024
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Different Current Measurement
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1
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7
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July 16, 2025
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Error during steady state analysis
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4
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24
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July 15, 2025
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Turn-On Losses at negative current using SiC (NVH4L018N0755C1)
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0
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9
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July 15, 2025
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How to receive only the last simulation time step (or last couple of cycles) from XML-RPC
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2
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25
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July 15, 2025
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DC-DC Bidirectional Buck boost converter
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1
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14
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July 15, 2025
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RT Box: Illegal transition conditions in forced commutation for topology 52_0
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7
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89
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July 15, 2025
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Space Vector PWM block for PLECS auto coding
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1
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14
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July 14, 2025
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Is it possible to change the Resistor in Simulation at a particular time point?
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6
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771
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July 14, 2025
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How to convert mosfets' LTspice model or Pspice model to plecs model?
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1
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45
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July 14, 2025
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Significant Discrepancy in SiC MOSFET Loss Calculation: Custom Script vs PLECS Lookup Table (C3M0021120K / C3M0015065K)
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7
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65
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July 11, 2025
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Full bridge DC DC converter
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2
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49
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July 10, 2025
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Different Result Between Plecs Blockset Simulation and Simulink
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9
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53
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July 9, 2025
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Transition from DAB with SPS DAB-LLC/CLLLC – Resonant Component Design and SPS Control
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1
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60
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July 8, 2025
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Algebraic loop involving PQ CONTROLLER
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1
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30
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July 8, 2025
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Output PWM signals from the Ti PWM Block within the controller/MCU
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4
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33
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July 8, 2025
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Unable to Compile C2000
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8
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134
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July 7, 2025
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The difference between DiscState and global variables in a C script.
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1
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15
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July 7, 2025
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Possibilities to change parameter in a simulation script used to calculate other paramters in the initialization file
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3
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32
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July 3, 2025
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Motor Winding (both delta and star)
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1
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21
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July 2, 2025
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Plecs Code Support
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3
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43
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July 2, 2025
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Voltage Source Average Model
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2
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35
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June 28, 2025
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PWM blocks with two different switching frequencies
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6
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79
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June 27, 2025
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Two LAUNCHXL-F28069M Synchronize issue
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7
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62
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June 26, 2025
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Task Sampling Time
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3
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43
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June 26, 2025
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Loop Gain Meter weird behaviour
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3
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52
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June 22, 2025
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Problems with application of ePWM block in Digital Control
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4
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82
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June 21, 2025
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Dual phase shift of dual active bridge DAB
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4
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95
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June 13, 2025
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I am currently working on building my RT Box coder for implementing phase shift modulation in a three-phase dual active bridge design. As part of the process, I need to generate a phase delay of 60° between each signal. Despite trying various approaches w
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7
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99
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June 13, 2025
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ZOH and sensing issue by using plecs
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4
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48
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June 13, 2025
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