|
Welcome to PLECS User Forum! :wave:
|
|
0
|
1354
|
July 4, 2024
|
|
Dual-CPU targets (F28P65x) – GPIO direction
|
|
0
|
8
|
August 23, 2026
|
|
HERIC Inverter Loss Analysis in PLECS
|
|
0
|
10
|
August 23, 2026
|
|
Matrix Converter - Cyclic Behaviour
|
|
3
|
96
|
August 20, 2026
|
|
Op-Amps and State Space Extraction
|
|
5
|
44
|
August 19, 2026
|
|
Droop control Problem Simulation
|
|
0
|
41
|
August 12, 2026
|
|
Question about MOSFET switching loss with external Coss and custom commutation current in PLECS 4.7.4
|
|
1
|
58
|
August 10, 2026
|
|
Positive Negative sequence seperation with DDSRF
|
|
1
|
29
|
August 10, 2026
|
|
Dual active bridge-cf
|
|
11
|
174
|
August 10, 2026
|
|
Processing Bitstream from Delta-Sigma Modulator
|
|
2
|
76
|
August 7, 2026
|
|
Carrier-peak synchronized sampling using the PWM Out block on RT Box
|
|
5
|
78
|
August 6, 2026
|
|
How to Generate the Optimal Inner and Outer Phase Shifts for Extended Phase Shift Modulation in a Series Partial-Power Dual Active Bridge Converter?
|
|
0
|
44
|
August 5, 2026
|
|
How to quantify the time delay of a RT BOX Controller?
|
|
2
|
862
|
August 4, 2026
|
|
Upgrading student licence to a newer version
|
|
1
|
33
|
August 3, 2026
|
|
Assistance with adapting DAB for RTBox HIL
|
|
10
|
133
|
July 31, 2026
|
|
Does PLECS interpolate the loss model between temperatures if the device's thermal model is only provided for certain temperatures?
|
|
2
|
48
|
July 29, 2026
|
|
Discrepancy between heat flow and conduction loss in thermal model
|
|
6
|
65
|
July 29, 2026
|
|
Issue Simulating Infineon CoolSiC MOSFET Models in PLECS 5.0.6
|
|
2
|
78
|
July 29, 2026
|
|
Complementary PWMs on different channels STM32
|
|
1
|
38
|
July 28, 2026
|
|
Inquiry Regarding Hardware-in-the-Loop (HIL) Simulation Issues
|
|
3
|
61
|
July 28, 2026
|
|
Support for the TMS320F28P551x
|
|
1
|
67
|
July 27, 2026
|
|
Seeking 12-pulse Cycloconverter Reference Model or C-Script for Cosine Intersectional Control
|
|
1
|
56
|
July 27, 2026
|
|
Simulating Verilog Logic in PLECS via Verilator
|
|
0
|
48
|
July 23, 2026
|
|
Why is my conduction loss so low—only 0.9 W?
|
|
1
|
43
|
July 23, 2026
|
|
Glitch in Variable Phase PWM block?
|
|
5
|
1836
|
July 21, 2026
|
|
I want to add a carrier delay in SVPWM in PLECS demo named three phase voltage source inverter
|
|
3
|
49
|
July 20, 2026
|
|
Assistance with Modified Thermal XML Model for Parallel IGBT Modules
|
|
3
|
83
|
July 19, 2026
|
|
Update software to newest version 5.0 , but have some trouble
|
|
3
|
80
|
July 18, 2026
|
|
Cyclic behavior during switching below D = 0.67 in Quadratic Buck-Boost Converter
|
|
3
|
60
|
July 17, 2026
|
|
Principle of switch loss of probe module
|
|
7
|
1378
|
July 17, 2026
|